Memory agent core clock aligned to lane

Static information storage and retrieval – Hardware for storage elements

Reexamination Certificate

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C365S063000, C365S233100

Reexamination Certificate

active

10858850

ABSTRACT:
Memory apparatus and methods align a core clock for a memory agent to one of a plurality of lanes. A memory agent may have logic circuit between the lanes and a core clock generator to align the core clock to one of the lanes. A deskew circuit may be coupled to the logic circuit. Other embodiments are described and claimed.

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