Memory addressing scheme for increasing the number of memory loc

Details Memory addressing scheme for increasing the number of memory loc Memory addressing scheme for increasing the number of memory loc

1995-05-24

1998-06-23

Eng, David Y.

Boots, shoes, and leggings

364955, 3642551, G06F 1210

Patent

active

057713685

ABSTRACT:
A backward compatible addressing scheme for increasing the number of memory locations available in a computer for storing higher precision numbers. The computer system of the present invention has a processor capable of manipulating numbers having precision S, where S is a power of 2. The memory locations are specified in an instruction address field by an n-bit logical address ##EQU1## Each S-precision number is stored in a group of S memory locations accessed by an m-bit physical address ##EQU2## Each memory location is capable of storing a single precision number. Addressing logic for addressing the memory locations with the logical addresses includes alignment logic for setting:

REFERENCES:
patent: 4361868 (1982-11-01), Kaplinsky
patent: 4482952 (1984-11-01), Akagi
patent: 4800489 (1989-01-01), Moyer et al.
patent: 4827400 (1989-05-01), Dunwell et al.
patent: 4970642 (1990-11-01), Yamamura
patent: 5109334 (1992-04-01), Kamuro
patent: 5249280 (1993-09-01), Nash et al.
patent: 5317706 (1994-05-01), Pechter
IBM Technical Disclosure Bulletin vol. 16, No. 3, Aug. 1973, New York, US, pp. 771-772 K. W. Stevens "Addressing a Second Page of registers Without Increasing the Register Field Length" *the whole documet*.
Patent Abstracts of Japan; vol. 7, No. 260 (P-237) (1405) 18 Nov. 1983 & JP-A-58 142 464 (Hitachi Seisakusho K.K.) 24 Aug. 1983 *abstract*.
IBM Technical Disclosure Bulletin; vol. 16, No. 3, Aug. 1973, New York US, pp. 771-772; K.W. Stevens' Addressing a Second Page Registers Without Increasing the Register Field Length' *the whole document*.
Hewlett-Packard Journal; vol. 37, No. 8, Aug. 1986, Palo Alto US pp. 4-21; M.J. Mahone et al., 'Hewlett-Packard Precision Architecture: The Processor' *p. 8, left col.,line 5 paragraph 5-9*.

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