Memory addressing apparatus for block scan and raster scan and a

Computer graphics processing and selective visual display system – Computer graphic processing system – Integrated circuit

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348718, G06F 1206

Patent

active

059823968

ABSTRACT:
Memory addressing apparatus and method for block scan and raster scan in an apparatus for processing image data of which the horizontal resolution is H and the vertical resolution is V. The memory addressing apparatus includes a horizontal counter for outputting a value sequentially incremented by a write or read signal for storing or reading image data in or from the memory, a vertical counter for outputting a value sequentially incremented by a horizontal synchronizing signal included in the image data, and an address generator for generating an address for raster scan or block scan according to a control signal by the horizontal and the vertical count values. Accordingly, memory address generating functions for raster scan and block scan are integrated into one unit, thereby the amount of required hardware is reduced, and simple design and structure of the apparatus reduce manufacturing cost.

REFERENCES:
patent: 5343243 (1994-08-01), Maeda
patent: 5428395 (1995-06-01), Jeong
patent: 5455908 (1995-10-01), Ishida
patent: 5517666 (1996-05-01), Ohtani et al.
patent: 5563662 (1996-10-01), Kishi

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