Memory address sequence generator

Details Memory address sequence generator Memory address sequence generator

1982-03-05

1984-04-10

Atkinson, Charles E.

Excavating

371 21, 324 73R, G11C 2900, G01R 3128

Patent

active

044425198

ABSTRACT:
Apparatus consisting of combinations of interconnected logic elements for generating preselected sequences of addresses for the listing of a matrix memory as a function of preset constants and variable timing impulses, wherein there are first and second X and Y address generators with controlled selection means for selecting the first or the second of the X and Y address pairs, each of the address generators being settably controllable to generate a preselected sequence of addresses in ascending or descending order, with settable increments within the sequence, settable masking, and settable displacements from a fixed reference origin.

REFERENCES:
patent: 4263669 (1981-04-01), Staiger
patent: 4300234 (1981-11-01), Maruyama
patent: 4370746 (1983-01-01), Jones
patent: 4389723 (1983-06-01), Nigorikawa

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