Memory address preview control circuit

Details Memory address preview control circuit Memory address preview control circuit

1996-08-27

1998-05-05

Nelms, David C.

Static information storage and retrieval

Addressing

Plural blocks or banks

365239, G11C 800

Patent

active

057485550

ABSTRACT:
A memory, and associated method of operating the memory, for use with a computer, the memory receiving address information from the computer via an address bus. The memory includes: an odd-address block of memory cells; an even-address block of memory cells; and an enablement circuit for simultaneously enabling either the odd-address block or the even-address block to be read from or written into and enabling a non-data exchange operation, i.e., a memory location access, in the other memory cell block that takes place while the other memory cell block is disabled to read or write. The simultaneous operations in the odd-address block and in the even-address block take place at the same location (in some instances) and at different locations (in other instances) so that, in the circumstance where the computer directs operations to take place upon sequential memory locations, the data at the second address is pre-accessed and available as soon as the address changes from the first address to the second address, which reduces overall memory access time.

REFERENCES:
patent: 3846765 (1974-11-01), De Vries
patent: 4247920 (1981-01-01), Springer et al.
patent: 5247644 (1993-09-01), Johnson et al.
patent: 5261064 (1993-11-01), Wyland
patent: 5453957 (1995-09-01), Norris et al.
patent: 5497355 (1996-03-01), Mills et al.

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