Memory address circuit having function of exchanging selected bi

Static information storage and retrieval – Read only systems – Semiconductive

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G06F 900

Patent

active

048315877

ABSTRACT:
A memory associated with an address circuit receiving an address signal to designate a location of the memory to be accessed. The address circuit includes an X-decoder and a Y-decoder associated to the memory, and a multiplexor receiving at least a portion of an address input and adapted to selectively distribute the above portion of the address input to the X-decoder and the Y-decoder. Specifically, the multiplexor receives at least one first bit of a portion of the address signal to be inputted to the X-decoder and at least one second bit of the remaining portion of the address signal to be iputted to the Y-decoder. In a first condition, the multiplexor operates to supply the first bit and the second bit of the address input to the X-decoder and the Y-decoder, respectively. In a second condition, the multiplexor operates to supply the first bit and the second bit of the address input to the Y-decoder and the X-decoder, respectively.

REFERENCES:
patent: 4651275 (1987-03-01), McDonough

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