Memory address and display control apparatus for high definition

Details Memory address and display control apparatus for high definition Memory address and display control apparatus for high definition

1993-12-28

1995-11-21

Groody, James J.

Television

Image signal processing circuitry specific to television

With details of static storage device

348716, 348407, 348431, H04N 712, H04N 1102

Patent

active

054692288

ABSTRACT:
A memory address and display control apparatus for an high definition television comprising a memory address controller for controlling memory read/write addresses in response to a motion vector and a control signal, the memory address controller having a display read control circuit, a motion compensation read control circuit, and a raster format write control circuit, a memory unit having a previous frame memory for storing a video signal of a previous frame and a present frame memory for storing a video signal of a present frame, a multiplexing circuit for 2 to 1-multiplexing the output addresses from the memory address controller to alternately address the previous frame memory and the present frame memory in the memory unit, an input/output controller for controlling data input/output of the memory unit in response to frame and invert frame signals, a display controller for receiving video data from the memory unit under the control of the input/output controller and displaying the received video data, and a motion compensation circuit for receiving previous frame video data from the memory unit under the control of the input/output controller and adding a DCT coefficient to the received previous frame video data to transform the received previous frame video data into present frame video data.

REFERENCES:
patent: 4403250 (1983-09-01), Kellar
patent: 4899220 (1990-02-01), Basile et al.
patent: 4982288 (1991-01-01), Isobe et al.
patent: 5093720 (1992-03-01), Krause et al.
patent: 5103295 (1992-04-01), Uwabata et al.

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