Memory accessing

Details Memory accessing Memory accessing

1990-03-16

1991-07-30

Popek, Joseph A.

Static information storage and retrieval

Addressing

Plural blocks or banks

365194, 365233, 365203, 365239, G11C 700, G11C 800

Patent

active

050364944

ABSTRACT:
A line delay device comprises a memory having RAM cells in two blocks, each cell being connected to a pair of bit lines. Memory locations in one block are addressed sequentially and subject to a data transfer while an equate operation is effected on the bit lines of the other block. The operations are switched alternately between the two blocks. In each accessing cycle, a plurality of locations are addressed in selected rows of each block and the switching between each block is effected without addressing all locations in each row addressed so that the accessing cycle ends in a different block from the starting block and each row used has a plurality of addressed locations.

REFERENCES:
patent: 4740923 (1988-04-01), Kaneko et al.
patent: 4849937 (1989-07-01), Yoshimoto

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