Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2007-09-11
2007-09-11
Peikari, B. James (Department: 2189)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S189011, C711S001000
Reexamination Certificate
active
09772830
ABSTRACT:
A memory system (200) has an array of addressable storage elements (210) arranged in a plurality of rows and a plurality of columns, and decoding circuitry (220, 230) coupled to the array of addressable storage elements (210). The decoding circuitry (220, 230), in response to decoding a first address, accesses a first storage element of a first row of the plurality of rows, and, in response to decoding a second address consecutive to the first address, accesses a second storage element of a second row of the plurality of rows. The second row of the plurality of rows is different from the first row of the plurality of rows. By implementing a memory system wherein consecutive addresses correspond to storage elements of different rows, read disturb stresses along a single row can be minimized.
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Baker, Jr. Frank K.
Burnett James D.
Jew Thomas
Freescale Semiconductor Inc.
Peikari B. James
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