Memory access system with overwrite prevention for overlapping w

Details Memory access system with overwrite prevention for overlapping w Memory access system with overwrite prevention for overlapping w

1996-12-16

1997-11-11

Swann, Tod R.

Excavating

39518204, 39518504, G06F 1100, G06F 1126

Patent

active

056871830

ABSTRACT:
The present invention operates within a data processing system including a processor coupled to a memory controller unit which is coupled to memory used for storing and retrieving data. The memory controller unit provides separate read and write data pipelines, allowing write operations to overlap preceding read operations. The present invention selectively delays a certain limited number of write operations, delaying a write operation only if it is directed to the same memory address as that of a preceding read operation. By delaying this limited number of write operations, the present invention substantially preserves the advantages of write overlap while preventing the problem of overwrite. An alternative embodiment of the present invention selectively suppresses error writeback operations associated with a read operation if the read operation is followed by a write operation to the same address.

REFERENCES:
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patent: 5101478 (1992-03-01), Fu et al.
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patent: 5155843 (1992-10-01), Stamm et al.
patent: 5197144 (1993-03-01), Edenfield et al.
patent: 5218711 (1993-06-01), Yoshida
patent: 5220312 (1993-06-01), Lumelsky et al.
Microsoft Press Computer Dictionary, Microsoft Press, 2nd ed., 1993 p. 419.
Microsoft Press.RTM. Computer Dictionary, 2nd ed., pp. 58-59.

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