Memory access system utilizing address translation

Details Memory access system utilizing address translation Memory access system utilizing address translation

1988-09-28

1990-06-26

Zache, Raulfe B.

Boots, shoes, and leggings

3642384, 3642563, 3642564, G06F 1210

Patent

active

049377353

ABSTRACT:
In a memory access system used for receiving a logical address and a memory request, translating the logical address into a real address, and accessing a memory by using the real address, a non-address-translation portion, which is not an object to be translated, in the logical address is transmitted in advance to the memory through an address signal line when the memory request associated with the logical address supplied to the memory is generated, and an address-translation portion, which is an object to be translated, in the logical address is transmitted to the memory through the address signal line upon completion of address translation of the address-translation portion.

REFERENCES:
patent: 4563737 (1986-01-01), Nakamura et al.
patent: 4763250 (1988-08-01), Keshlear et al.

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