Memory access system for pipelined data paths to and from storag

Details Memory access system for pipelined data paths to and from storag Memory access system for pipelined data paths to and from storag

1989-09-06

1991-10-22

Bowler, Alyssa H.

Boots, shoes, and leggings

36518904, 36523003, 36523005, G11C 700, G06F 700, G06F 1300

Patent

active

050601458

ABSTRACT:
A novel memory access system is provided for simultaneously processing request for access to a plurality of memory banks. A plurality of input-output ports are coupled to a read bus and to a write bus which are in turn coupled to the memory banks to be accessed by read and write commands initiated by processors coupled to the I/O ports. Pipeline control means receive the request for access functions from the processors and are operable to resolve conflict between plural request. The pipeline control means sequentially raise either write or read request on control and address buses and generate time slot windows during which subsequent write or read data transfer operations will occur so that data being pipelined on the write and read buses is being simultaneously accessed.

REFERENCES:
patent: 3573854 (1971-04-01), Watson et al.
patent: 4731724 (1988-03-01), Michel et al.
patent: 4845677 (1989-07-01), Chappell et al.
patent: 4853896 (1989-08-01), Yamaguchi
patent: 4891795 (1990-01-01), Pinkham et al.

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