Memory access optimization

Details Memory access optimization Memory access optimization

2008-11-07

2010-10-26

Mattis, Jason E (Department: 2461)

Multiplex communications

Diagnostic testing

Determination of communication parameters

C370S250000, C370S253000

Reexamination Certificate

active

07821962

ABSTRACT:
A method and an apparatus for memory access optimization are disclosed. Data unit information may be accumulated for a plurality of data units. Partial network statistics for the plurality of data units may be read sequentially in round robin fashion from each of a plurality of memory banks of a memory. The partial networks statistics may be updated based on the plurality of data units. The updated partial network statistics may be written sequentially in round robin fashion to each of the plurality of memory banks.

REFERENCES:
patent: 5742760 (1998-04-01), Picazo, Jr. et al.
patent: 5805927 (1998-09-01), Bowes et al.
patent: 5850386 (1998-12-01), Anderson
patent: 5982753 (1999-11-01), Pendleton et al.
patent: 6065053 (2000-05-01), Nouri et al.
patent: 6088777 (2000-07-01), Sorber
patent: 6938133 (2005-08-01), Johnson et al.
patent: 7002980 (2006-02-01), Brewer et al.
patent: 7007089 (2006-02-01), Freedman
patent: 7035223 (2006-04-01), Burchfiel et al.
patent: 7187683 (2007-03-01), Sandoval et al.
patent: 7443836 (2008-10-01), Hooper
patent: 7443870 (2008-10-01), Zioulas
patent: 2002/0183969 (2002-12-01), Hanes et al.
patent: 2003/0033025 (2003-02-01), Lee et al.
patent: 2004/0252686 (2004-12-01), Hooper
patent: 2006/0153078 (2006-07-01), Yasui
patent: 2007/0115833 (2007-05-01), Pepper
patent: 2007/0291654 (2007-12-01), Pepper
patent: 2008/0112332 (2008-05-01), Pepper
US Patent and Trademark Office, Office Action dated Mar. 19, 2009 for U.S. Appl. No. 11/424,832, filed Jun. 16, 2006.
United States Patent and Trademark Office, Final Office Action for U.S. Appl. No. 11/424,832, Mail Date Mar. 17, 2010.
USPTO, Office Action for U.S. Appl. No. 11/424,832, Mail Date May 4, 2010.
Ixia, IxExplorer User's Guide, Revision 2.1.0, Nov. 1, 1999.
Ixia, Product Specification Sheet, “Specifications for Load Modules—Multilayer Gigibit Ethernet for LM1000LX, LM1000SX, LM1000GBIC, LM1000T,”, 1999.
Ixia, Product Description, “The Ixia 200 Traffic Generator and Analyzer,” 1997-1999.
Ixia, Product Description, “Ixia 200 Chassis,”, 1999.

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