Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
1998-11-17
2002-07-09
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S230030
Reexamination Certificate
active
06418077
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to memory access methods and devices for use with random access memories and, in particular but not exclusively, with synchronous dynamic random access memories (SDRAMs).
2. Description of the Related Art
SDRAM devices are designed so as to be simpler to use than standard dynamic random access memories (DRAMs) which suffer from many control signal timing constraints. The data bandwidth of such an SDRAM device may be as much as 5 times that of a standard DRAM, making the SDRAM device ideally suited for use in, for example, laser printers, high resolution graphic adapters, accelerators, and other applications where an extremely large memory and bandwidth are required.
A typical organisation of an SDRAM device is shown in
FIG. 1
of the accompanying drawings. Such a device is described, for example, in detail in “Product Profile Sheet: MB811171622A CMOS 2×512 K×16 Synchronous DRAM”, Fujitsu Limited, July 1996.
At the core of the SDRAM device
1
are two banks
2
and
3
, each of which is constituted by a matrix of memory cells. In each bank, the matrix is organised to provide storage for 512 K words of 16 bits (K=1024). A total of 20 address input signals are required to identify a particular word in one of the banks
2
or
3
. To reduce the pin count of the device, an 11-bit row address A
0
to A
10
is supplied first to an address buffer/register
4
of the device, whereafter an 8-bit column address A
0
to A
7
is applied to the address buffer/register
4
. A further address bit A
11
is used as a bank select signal for selecting either the first bank
2
or the second bank
3
of the device.
The SDRAM device
1
further comprises a clock buffer
5
, command decoder
6
, input/output data buffer/register
7
, control signal latches
8
and
9
corresponding respectively to the two banks
2
and
3
, a mode register
10
, and column address counters
11
and
12
corresponding respectively to the banks
2
and
3
. The constitution and operation of the elements of the SDRAM device
1
shown in
FIG. 1
are well-known in the art and so will not be described further herein.
There are three major differences between the SDRAM device
1
and a conventional DRAM. The first, and most important, difference is that the SDRAM operates synchronously using a clock input for synchronisation purposes, whereas the conventional DRAM is essentially an asynchronous memory device even though it makes use of timing signals RAS and CAS. In the conventional DRAM, each operation is determined by the phase differences between these two timing signals, whereas in the SDRAM device
1
of
FIG. 1
, each operation is determined by commands and all operations are referenced to a positive clock edge.
The SDRAM device
1
of
FIG. 1
also differs from the conventional DRAM in that it is capable of operating in a burst mode which is a very high speed access mode (read or write) utilising the internal column address counters
11
and
12
. Once a column address for the first access is set, the following addresses are automatically generated by one of the internal column address counters
11
or
12
.
Further, the SDRAM device
1
of
FIG. 1
differs from the conventional DRAM in having the mode register
10
which serves to configure the SDRAM operations and functions so as to achieve desired system conditions.
Each bank
2
or
3
in
FIG. 1
contains multiple pages, for example there may be 2 K pages, each containing 256 words. To access (read or write) an item of information within a page, the bank containing the page must be in a defined state, i.e. the bank must have been precharged, and the page must have been activated. These precharge and activation operations require clock cycles. Accordingly, a precharge is best carried out when accessing of one page is finished with, so that the next page is then ready for immediate activation when required.
As mentioned above, SDRAM devices are synchronous devices, and actions are carried out on the positive clock edge. An SDRAM device can be programmed to process commands after n clock cycles (n=1, 2 or 3), and n=3 usually enables the highest throughput.
Information can be accessed in bursts, but (unfortunately for ease of use) the leading and trailing parts (protocols) of the access sequence differ between reads and writes. The burst length can be programmed, but is usually set to either 4 or 8 words, particularly when the accesses are relatively short and random. Bursts can be terminated automatically by precharge commands, or these can be issued explicitly. Automatically terminated read bursts give performance advantages, but automatically terminated write bursts do not (in this case the automatic precharge command simply eliminates the need to issue an explicit precharge command).
Bursts that are not automatically terminated by precharge can be interrupted and terminated by other bursts, but it is best to terminate reads with reads and writes with writes, and to ensure that the final burst access is of the automatically precharged type.
SDRAM devices naturally achieve high throughputs of information if the burst lengths are greater than eight words (sufficient to hide the leading and trailing read and write access protocols), and banks can be continually interleaved. However, these criteria are not easy to achieve in some of the applications in which SDRAM devices are normally considered for use. For example, in asynchronous transfer mode (ATM) communication systems, SDRAM devices are considered attractive for storing information items (e.g. transient control parameters) relating to ATM cells. If the ATM cells are to be processed at rates of 622 MHz or higher, the cell lifetimes are relatively short, for example 680 ns. The processing of cells is normally pipelined, so that, within a single ATM cell lifetime (680 ns), it may be necessary to write one or more information items and to read one or more information items. To secure the expected benefits (e.g. performance and memory depth) of SDRAM devices in such demanding situations, it is therefore desirable to provide improved methods and devices for accessing information items stored in SDRAM devices.
The same requirements can arise in random access memory systems not employing SDRAM devices. For example, so-called Rambus devices are commercially available (example devices are the NEC uPD488130L and the Toshiba TC59R0808HK) which, in common with SDRAM devices, have two (or more) banks which share a common data bus. Rambus DRAMs (or RDRAMS) are developed and marketed by Rambus Inc., a high-speed interface technology company, and can transfer data at 600 megabytes per second or more over a so-called Rambus Channel, a narrow byte-wide data bus. Rambus DRAMs can provide 8 times the bandwidth per pin of alternative high-speed DRAM components. Rambus memories are accessed using protocols that require a relatively high number of clock cycles to initiate the access (even more than SDRAM devices). In these Rambus devices, additional clock cycles also elapse before the data starts to be transferred. To try to maintain high effective throughput rates, the size of the data transfer (burst) is usually about 32 or more bytes. Furthermore, SyncLink devices (SyncLink is a consortium of DRAM manufacturers whose goal is to create an industry standard for a new DRAM architecture which allows data transfer rates of 500 Mbytes up to 3.2 Gbytes per second) are random access memory devices with a single input/output of high bandwidth which also use protocols broadly similar to Rambus protocols.
Even in the case of random access memory systems which do not employ plural-bank individual devices (such as SDRAM devices or Rambus devices) there may arise a demand to read one or more information items from the memory and to write one or more information items to the memory in the same time slot, the duration of this time slot being less than the total time required to access the items sequentially. For example, such a
Fujitsu Limited
Nelms David
Staas & Halsey , LLP
Tran M.
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