Memory access method and apparatus in multiple processor systems

Details Memory access method and apparatus in multiple processor systems Memory access method and apparatus in multiple processor systems

1984-02-10

1985-12-24

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1300, G06F 1516

Patent

active

045610517

ABSTRACT:
A multiprocessor data processing system in which a number of independent processors can concurrently operate on a shared memory even when one processor is performing a read-modify-write (RMW) operation, the system having a locking, content-associative write buffer and a controller for identifying RMW requests, for addressing the buffer and, for issuing directives to lock the buffer, to validate particular data blocks in the buffer and to transfer data back and forth between the processors, the memory and the buffer.

REFERENCES:
patent: 3108257 (1963-10-01), Buchholz
patent: 3435418 (1969-03-01), Evans et al.
patent: 3469239 (1969-09-01), Richmond et al.
patent: 3508205 (1970-04-01), Kubie
patent: 3528061 (1970-09-01), Zurcher
patent: 3551892 (1970-12-01), Driscoll
patent: 3568157 (1971-02-01), Downing et al.
patent: 3573736 (1971-04-01), Schlaeppi
patent: 3631405 (1971-12-01), Hoff
patent: 3706077 (1972-12-01), Mori et al.
patent: 3725872 (1973-04-01), Balough et al.
patent: 3761883 (1973-09-01), Alvarez et al.
patent: 3771146 (1973-11-01), Cotton et al.
patent: 4000485 (1976-12-01), Barlow et al.
patent: 4037215 (1977-07-01), Birney et al.
patent: 4038645 (1977-07-01), Birney et al.
patent: 4050059 (1977-09-01), Williams et al.
patent: 4073005 (1978-02-01), Parkin
patent: 4099243 (1978-07-01), Palumbo
patent: 4136386 (1979-01-01), Annunziata et al.
patent: 4162529 (1979-07-01), Suzuki et al.
patent: 4214304 (1980-07-01), Shimizu et al.
patent: 4245306 (1981-01-01), Besemer et al.

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