Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2002-11-04
2004-08-17
Tran, M. (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S230010
Reexamination Certificate
active
06778463
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a memory access interface, and more specifically to a memory access interface in which a memory is shared between a micro-controller having an address/data multiplexing bus and a microprocessor.
2. Description of the Related Art
In order to reduce the number of I/O pins in some micro-controllers, such as micro-controllers of the 80C32 series, a set of output pins are shared between a data bus and a lower-bit address bus.
FIG. 1
shows a typical memory system having a micro-controller and the address/data multiplexing bus. Referring to
FIG. 1
, the micro-controller
11
utilizes an address latch
12
to latch the lower-bit address signal A
7
:
0
of the address/data multiplexing bus A
7
:
0
/D
7
:
0
when the address-latch-enable signal ALE is enabled. The address signal A
7
:
0
together with the higher-bit address signal A
15
:
8
are inputted to the address bus of the memory
13
. The reading signal /READ of the micro-controller
11
is transferred to the output-enabling control terminal OE of the memory
13
so as to enable or disable the output of the memory
13
. When the reading signal /READ is enabled, the output from the memory
13
is also enabled, and the data corresponding to the address signal A
15
:
0
is transferred to the data bus D
7
:
0
. The micro-controller
11
accesses the data of the data bus D
7
:
0
of the memory through the address/data multiplexing bus A
7
:
0
/D
7
:
0
.
FIG. 2
shows a typical timing diagram during the accessing cycle of the micro-controller
11
. As shown in
FIG. 2
, the accessing cycle of the micro-controller
11
is divided into an address phase and a data phase. The address-latch-enable signal ALE is enabled in the address phase, while the reading signal /READ is enabled in the data phase.
Because the memory in the memory system can only be accessed by a single micro-controller, the efficiency of the memory is poor. Therefore, the efficiency of the memory can be improved if two or more microprocessors are capable of sharing the memory.
SUMMARY OF THE INVENTION
In view of the above-mentioned problems, an object of the invention is to provide a memory access interface capable of sharing a memory between a micro-controller having an address/data multiplexing bus and one or more microprocessors.
To achieve the above-mentioned object, the memory access interface of the invention includes an address latch, a multiplexer, and a data buffer. The address latch receives a signal of the address/data multiplexing bus of the micro-controller and an address-latch-enable signal, and latches the signal of the address/data multiplexing bus and outputs the lower-bit address signal when the address-latch-enable signal is enabled. The multiplexer receives the lower-bit address signal outputted from the address latch, a higher-bit address signal outputted from the micro-controller, and an address signal outputted from a microprocessor. The multiplexer is controlled by a first control signal of the micro-controller so as to provide the address signal of the micro-controller or the address signal of the microprocessor to the memory. The data buffer receives the signal of the data bus of the memory and is controlled by a second control signal of the micro-controller, for outputting the signal of the data bus to the address/data multiplexing bus of the micro-controller during a data phase of the micro-controller, and for keeping the output of the data buffer at a high impedance state during an address phase of the micro-controller.
REFERENCES:
patent: 5355348 (1994-10-01), Ooishi
patent: 5931930 (1999-08-01), Krick et al.
patent: 6192451 (2001-02-01), Arimilli et al.
Mediatek Inc.
Tran M.
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