Memory access device

Details Memory access device Memory access device

1994-10-17

1996-03-19

Nguyen, Viet Q.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36523001, 365239, 395427, G06F 1300

Patent

active

055008305

ABSTRACT:
In a memory access device, each of read and write addresses generated by read and write address generating means is stored in a read or write address buffer through a read or write address latch. The memory is accessed based on an address supplied by either address buffer from the bottom side thereof. Each address generating means is arranged such that, when a generated address is stored in the corresponding address buffer, the address calculation stage is finished. Exception detecting means is arranged to conduct exception detection on each address before the address is supplied from the corresponding address buffer, i.e., while the address is being latched by the corresponding address latch. Accordingly, the exception detection on each address can be conducted independently from a pipeline operation, thus shortening the execution time of each calculation stage. This prevents the calculation stage from forming a critical path.

REFERENCES:
patent: 4599362 (1986-07-01), Kinjo et al.
patent: 4763294 (1988-08-01), Fong
patent: 4970641 (1990-11-01), Hester et al.

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