Memory access control unit for allowing maximum throughput of an

Details Memory access control unit for allowing maximum throughput of an Memory access control unit for allowing maximum throughput of an

1990-06-04

1993-08-10

Dixon, Joseph L.

Boots, shoes, and leggings

364DIG1, 36424341, 36493146, G06F 1200

Patent

active

052356884

ABSTRACT:
When an IOP is transferring data at the maximal throughput because of the fact that the input-output processor (IOP) has issued a next request under a state when the request buffers are full of requests from the IOP at least a part of the requests from the instruction processor (IP) is inhibited. Inhibition of the requests from the IP is released when the pitch of the requests from the IOP reaches a predetermined period or more. When the IOP is transferring data at the maximal throughput in a system having a cache memory, access to the main memory by the IP is inhibited in case requested data does not exist in the cache memory.

REFERENCES:
patent: 3648252 (1972-03-01), Thron et al.
patent: 3954948 (1990-09-01), Hira et al.
patent: 4152761 (1979-05-01), Louie
patent: 4646233 (1987-02-01), Weatherford et al.
patent: 4648065 (1987-03-01), Zenk et al.
patent: 4665483 (1987-05-01), Ciacci et al.
patent: 4835672 (1989-05-01), Zenk et al.
patent: 4873629 (1989-10-01), Harris et al.
patent: 4942518 (1990-07-01), Weatherford et al.
patent: 5140682 (1992-08-01), Okura et al.

Affiliated with

Also associated with

Rating

Memory access control unit for allowing maximum throughput of an does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory access control unit for allowing maximum throughput of an, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory access control unit for allowing maximum throughput of an will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1732443