Memory access control system which prohibits a memory access req

Details Memory access control system which prohibits a memory access req Memory access control system which prohibits a memory access req

1992-09-30

1997-04-22

Elmore, Reba I.

395250, 395280, 395287, 395308, 395405, G06F 1320

Patent

active

056236220

ABSTRACT:
A memory access control system which performs a DMA transfer and allows a central control unit to perform a specific, required software operation. A central control unit sets a flag after running the specific software operation. The DMA transfer includes a first phase and a second phase, the first phase being a first transfer between a main memory and a first buffer memory and then a successive, second transfer between the main memory and a second buffer memory. The second phase is a transfer between a respective buffer memory and an external memory. A first DMA controller requests the first phase and controls the transfer of the second phase from a respective buffer memory when a transfer of the first phase from the main memory to the respective buffer memory ends, and prohibits a request for the first phase when the first transfer ends during a transfer of the second phase from the second buffer memory. A DMA request controller controls the request for the first phase and prohibits a request when the second transfer of the first phase ends and cancels the prohibition of a request when the flag of the central control unit is set. In response to a request for the first phase, an external bus control unit halts the operation of the central control unit and performs the first and second transfers of the first phase.

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