Memory access control device which can be formed by a reduced nu

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395425, G06F 1206, G11C 800

Patent

active

051013380

ABSTRACT:
In an access control device (30) for use in combination with first through (2.times.m)-th memory units (m: 2, 3, . . . ) each of which is assigned with at least one of addresses consecutively numbered among the memory units, each of first through m-th arithmetic circuits products, in response to a base address B of the addresses and a preselected distance D, an arithmetic result (B+nD), where n represents one of first through m-th values which are equal to "0", "1", . . . , and "m-1", respectively. A value distributing circuit (36) is preliminarily given the values and distributes the first through the m-th values in response to a distributing control signal. Responsive to the base address and to the preselected distance, a signal producing circuit (39) produces the distributing control signal. A result distributing circuit (43) distributes the arithmetic results of the first through the m-th arithmetic circuits to the first through the (2.times.m)-th memory units as selected ones of the addresses. The selected addresses are determined by selecting the base address in consideration of the preselected distance left between two adjacent ones of the selected addresses.

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