Memory access control apparatus and image pickup apparatus

Details Memory access control apparatus and image pickup apparatus Memory access control apparatus and image pickup apparatus

2009-06-18

2011-11-29

Villencco, John (Department: 2622)

Television

Camera, system and detail

Combined image signal generator and general image signal...

C711S105000, C711S106000, C365S233130

Reexamination Certificate

active

08068150

ABSTRACT:
A memory access control apparatus includes a memory controller controlling a memory adopting a DDR format; a DDR-PHY adjusting the timing of an interface signal between the memory controller and the memory; a DDR-PHY controller controlling the DDR-PHY; and a clock controller controlling the frequency of a clock signal. A first request signal for controlling the operation of the memory in a self-refresh mode is supplied to the memory controller, a second request signal for resetting the DDR-PHY is supplied to the DDR-PHY controller, a third request signal for changing the clock frequency is supplied to the clock controller, a fourth request signal for setting a parameter for the DDR-PHY is supplied to the DDR-PHY controller, and a fifth request signal for canceling the operation of the memory in the self-refresh mode is supplied to the memory controller in order to change the clock frequency of the memory.

REFERENCES:
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patent: 2004/0117565 (2004-06-01), Brant et al.
patent: 2005/0273564 (2005-12-01), Lakshmanamurthy et al.
patent: 2007/0067596 (2007-03-01), Yu et al.
patent: 2008/0247261 (2008-10-01), Ishikawa
patent: 2005-94294 (2005-04-01), None
patent: 2007-310549 (2007-11-01), None

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