Memory access circuit with address translation performing auto i

Details Memory access circuit with address translation performing auto i Memory access circuit with address translation performing auto i

1995-06-07

1997-12-09

Lane, Jack A.

395413, 39542109, G06F 1210

Patent

active

056969244

ABSTRACT:
A memory access system for use with a graphics processor having an address bus, a data bus and a set of control lines. An address translator circuit connected to the address bus of the graphics processor supplies a translated address to a memory upon receipt of an address from the graphics processor. A logic circuit responds to a write signal to automatically increment the translated address and responds to a control signal to return to the translated address. Control circuitry connected to the logic circuit responds to a read signal to supply the control signal to the logic circuit.

REFERENCES:
patent: 4503429 (1985-03-01), Schreiber
patent: 5129059 (1992-07-01), Hannah
patent: 5142672 (1992-08-01), Johnson et al.

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