Electrical computers and digital processing systems: multicomput – Network-to-computer interfacing
Reexamination Certificate
1999-03-29
2002-03-26
Vu, Viet D. (Department: 2154)
Electrical computers and digital processing systems: multicomput
Network-to-computer interfacing
C709S236000, C709S238000, C370S401000, C370S469000
Reexamination Certificate
active
06363432
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of local area networks. More particularly, the present invention relates to a technique for interfacing disparate transmission media in an IEEE 802.3 (Ethernet) local area network.
BACKGROUND OF THE INVENTION
The IEEE 802.3 standard for local area networks is often referred to as Ethernet. This standard allows network devices of various manufacturers, such as network interface cards (NICs), hubs, bridges, routers, and switches, to communicate packetized data with each other in a local area network (LAN). The IEEE 802.3 standard is defined in terms of the Open Systems Interconnection (OSI) reference model. This model defines a data communication system in terms of layers. Among the layers included in the OSI model are: (1) the physical layer (PHY), which specifies the electrical and coding characteristics of the transmission medium; (2) the medium access control (MAC) layer, which controls flow of data through the network; and (3) the network layer, which sets up connections between sources and destinations for data communicated in the network. Other layers include the transport layer, which is a protocol stack for transporting the data, and the application layer, such as a word-processor or spread sheet application.
A supplement to the 802.3 standard, for higher data transmission rates, is the 802.3u standard which often referred to as Fast Ethernet. This standard includes several physical layer (PHY) specifications, including 100BASE-TX (for Category 5 data grade unshielded twisted pair (UTP) cabling), 100BASE-FX (for fiber-optic cabling) and 100BASE-T4 (for Category 3 voice grade UTP). Each of these PHY specifications has its own advantages and disadvantages. For example, 100BASE-TX requires fewer UTP cables between network nodes than does 100BASE-T4, however, Category 5 UTP cabling is required for 100BASE-TX. Therefore, 100BASE-T4 may be more appropriate for a site which has existing Category 3 UTP cables in place for a telephone system. Further, the fiber-optic cables used for 100BASE-FX tend to be more costly than UTP cables, especially if UTP cables are already in place, however, fiber-optic cables allow for greater distances between network nodes. For example, 100BASE-TX or 100BASE-T4 can be an appropriate choice for LAN segments within a building, while 100BASE-FX can be an appropriate choice for connections between buildings. In addition, because fiber-optic cabling exhibits greater immunity to electrical noise than copper conductors, 100BASE-FX can be appropriate choice for electrically noisy environments. Therefore, it can be desirable for a single LAN to encompass more than one type of transmission media.
The 802.3u standard also includes a specification for a Medium-Independent Interface (MII) between the physical layer (PHY) and the medium access control (MAC) layer. Thus, a bridge for a Fast Ethernet network can include different transceivers for the different PHY layers, each of which communicates with a MAC layer of the bridge according to the MII specification. Fast Ethernet includes capability for simultaneous communication in two directions (full-duplex). Data is generally communicated serially over the transmission media in an Ethernet LAN, whereas, the MII specification requires parallel data communication. Therefore, a Fast-Ethernet transceiver typically performs serial-to-parallel conversion.
An example of a Fast Ethernet bridge
100
is illustrated in
FIG. 1. A
first 100BASE-TX transceiver
102
is coupled to a Category 5 UTP network segment
104
. The transceiver
102
is coupled to a control/buffer block
106
via an interface
108
. Similarly, a second 100BASE-TX transceiver
110
is coupled to a Category 5 UTP network segment
112
. The transceiver
110
is coupled to the control/buffer block
106
via an interface
114
. A 100BASE-FX transceiver
116
is coupled to a fiber-optic network segment
118
. The transceiver
116
is coupled to the control/buffer block
106
via an interface
120
. Each of interfaces
108
,
114
,
120
is in accordance with the MII standard. The bridge
100
receives data from the segments
104
,
112
,
118
, filters, stores and forwards the data to the segments
104
,
112
,
118
, as appropriate. To perform these functions, the control/buffer block
106
requires data processing and buffering capability.
Accordingly, the Fast Ethernet bridge
100
interconnects disparate transmission media. Due to its complexity, however, such a Fast Ethernet bridge
100
is relatively costly. Further, because the Fast Ethernet bridge buffers the data, transmission delays are introduced. Therefore, what is needed is an economical technique for interconnecting disparate transmission media in a Fast Ethernet LAN. What is further needed is a technique for interconnecting disparate transmission media in a Fast Ethernet LAN that minimizes transmission delays.
SUMMARY OF THE INVENTION
The invention is a technique for interfacing transmission media in a local area network (LAN). According to the present invention, physical layer devices, such as a first transceiver and a second transceiver, each have a media dependent interface and a media independent interface. The media dependent interface of each transceiver is coupled to respective transmission media while the media independent interface of each transceiver is coupled to the media independent interface of the other transceiver. Data received from the respective transmission media by one of the transceivers is passed directly to the media independent interface of the other transceiver without first being modified or buffered. This contrasts with prior techniques which require intermediate data processing and buffering between transceivers.
Each transceiver includes a reference clock input terminal and a receive clock output terminal. The reference clock input terminal is coupled to receive a reference clock signal which is utilized for clocking data into the transceiver from the media independent interface, for clocking data out from the transceiver to the media dependent interface, and which is utilized as a reference for a receive phase-locked loop (PLL). The receive PLL of each transceiver is locked to a data signal received from the transmission media via the media dependent interface and provides a phase-aligned clock signal to the receive clock output. For purposes of this document, a data signal can be either an idle signal or a content-containing signal. The phase-aligned clock signal is aligned in phase to the data signal received from the media dependent interface. When the transmission media is initially quiet, a delay period of time is required after the data signal is received from the media dependent interface for the phase-aligned clock signal to become aligned with it. In addition, each transceiver includes a status output terminal which provides a status signal. The status signal is active when the data signal is being received from the transmission media by the transceiver.
The receive clock output terminal of the first transceiver is coupled to a first input terminal of a first multiplexer logic. The receive clock output terminal of the second transceiver is coupled to a first input terminal of a second multiplexer logic. A fixed frequency clock signal is coupled to a second input terminal of the first multiplexer logic and to a second input terminal of the second multiplexer logic. An output terminal of the first multiplexer logic is coupled to the reference clock input terminal of the second transceiver, while an output terminal of the second multiplexer logic is coupled to the reference clock input terminal of the first transceiver. A select input terminal of the first multiplexer logic is coupled to the status output terminal of the first transceiver, while a select input of the second multiplexer logic is coupled to the status output terminal of the second transceiver. Preferably, a delay block having a delay equal to the delay required for the corresponding phase-aligned clock signal to become al
Haverstock & Owens LLP
Micro Linear Corporation
Vu Viet D.
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