Multiplex communications – Channel assignment techniques – Details of circuit or interface for connecting user to the...
Reexamination Certificate
1998-04-21
2001-08-14
Ton, Dang (Department: 2661)
Multiplex communications
Channel assignment techniques
Details of circuit or interface for connecting user to the...
C370S389000, C370S465000
Reexamination Certificate
active
06275501
ABSTRACT:
BACKGROUND
The present invention concerns data transfer over a network and pertains particularly to a media access controller capable of connecting to a serial physical layer device and a media independent interface physical layer device.
The IEEE 802.3 specification has been created and adopted as a method of sending information between computers and other devices. The IEEE 802.3u specification extended the technology for 100 megabits per second networking.
Within the IEEE 802.3 specification a physical sublayer (PHY) includes a Physical Coding Sublayer (PCS), a Physical Media Access (PMA) sublayer, and a Physical Media Dependent (PMD) sublayer. The PCS defines how data is encoded and decoded as well as how the Carrier Sense (CS) and Collision Detection (CD) functions work. The PCS also defines the interface between higher and lower layers in the protocol specification. The PMA defines the mapping of code bits, generation of a control signal (link_status), generation of control signals to the PCS, and clock recovery. The control signal (link_status) indicates the availability of the PMD. The control signals to the PCS indicate Carrier Sense, Collision Detection and Physical Layer Errors. The PMD defines the signaling method and parameters for the various physical parameters that are necessary to address the link's physical requirements.
The PHY is generally placed on a dedicated integrated circuit (chip). The PHY communicates with a separate media access control (MAC) integrated circuit. The MAC provides an interface to a host system. Some PHY chips provide connectivity for 10Base2 devices. For example, a PHY chip which provides connectivity to an attachment unit interface (AUI) (for 10Base2 connectivity) is available as part LXT908 from Level One Communications, Inc., having a business address of 9750 Goethe Road, Sacramento, Calif. 95827. PHYs which provide 10Base2 connectivity typically interface with a serial MAC chip.
With the advent of the IEEE 802.3u specification, some PHY chips provide connectivity to 10/100T networks. For example, a PHY chip which provides connectivity to 10/100 megabit networks is available as part LXT970 from Level One Communications, Inc. In order to connect a MAC chip to multiple PHY chips which can provide connectivity to 10/100 megabit networks or other types of media, a media independent interface (MII) bus was created. A PHY chip connected to an MII bus transmits to and receives data from a MAC chip in four bit groupings (nibbles) of data. For more information on construction of an MII bus, see Chapter 22 of the IEEE 802.3u specification.
Generally, to provide 10Base2 along with 10/100T connectivity, it is necessary to utilize two separate MACs. However Seeq Technology Inc. having a business address of 47200 Bayside Pky, Fremont, Calif. 94538-6567 has designed a specialized 10Base2 PHY which can communicate with a MAC over an MII bus. However, this solution requires the use of a specialized 10Base2 PHY.
SUMMARY OF THE INVENTION
In accordance with the preferred embodiment of the present invention, a network node is connectable to a network. The network node includes a serial physical sublayer (PHY) chip, a parallel PHY chip, and a media access control (MAC) chip. For example, the parallel PHY chip is a media independent interface (MII) PHY chip. The serial PHY chip, includes a single bit transmit data input, a single bit receive data output, and serial PHY control signal input/output (I/O) lines. The parallel PHY chip includes a multi-bit transmit data input, a multi-bit receive data output, and parallel PHY control signal I/O lines. The media access control chip includes a multi-bit transmit data output, a multi-bit receive data input and parallel control signal I/O lines. The multi-bit transmit data output is connected to the multi-bit transmit data input. One bit of the multi-bit transmit data output is connected to the single bit transmit data input. The multi-bit receive data input is connected to the multi-bit receive data output. One bit of the multi-bit receive data input is connected to the single bit receive data output. The parallel control signal I/O lines are connected to the parallel PHY control signal I/O lines.
In the preferred embodiment, the serial PHY control signal I/O lines are connected to a subset, but not all, of the parallel control signal I/O lines. Also, in the preferred embodiment, the single bit transmit data input, the single bit receive data output and the serial PHY control signal I/O lines of the serial PHY chip can be electrically isolated when data is being transmitted between the parallel PHY chip and the MAC chip.
Also, in the preferred embodiment, the MAC chip additionally includes a receive clock line on which is placed a receive clock signal. A receive shift register within the MAC chip is connected to the multi-bit receive data input, and to the receive clock signal. When the MAC chip receives data from the parallel PHY chip, the data is clocked into the receive shift register four bits at a time. When the MAC chip receives data from the serial PHY chip, the data from the serial PHY chip is clocked into the receive shift register one bit at a time. When the MAC chip receives data from the parallel PHY chip, the receive clock signal has a first frequency (e.g. 2.5 MHz or 25 MHz). When the MAC chip receives data from the serial PHY chip, the receive clock signal has a second frequency (e.g., 10 MHz).
Also, in the preferred embodiment, the MAC chip additionally includes a transmit clock line on which is placed a transmit clock signal. A transmit shift register within the MAC chip is connected to the multi-bit transmit data output, and to the transmit clock signal. When the MAC chip sends data to the parallel PHY chip, the data is clocked out of the transmit shift register four bits at a time. When the MAC chip sends data to the serial PHY chip, the data sent to the serial PHY chip is clocked out of the transmit shift register one bit at a time. The transmit clock signal has a first frequency (e.g. 2.5 MHz or 25 MHz) when the MAC chip transmits data to the parallel PHY chip, and has a second frequency (e.g., 10 MHz) when the MAC chip transmits data to the serial PHY chip.
The present invention reduces the cost of providing for simultaneous support of 10T, 100T and 10 base 2 connectivity. A single network card with only one MAC chip can be designed to provide all three connection options. Any MII compatible PHY can be connected simultaneously with any serial PHY. By connecting two PHY chips to a single MAC chip, it is possible to save printed circuit board space, and to conserve power consumption. Since the present invention allows compatibility with any serial PHY, it allows the use of any competitively priced 10Base2 PHY.
REFERENCES:
patent: 5821910 (1998-10-01), Shay
patent: 5852609 (1998-12-01), Adams, III et al.
patent: 5995514 (1999-11-01), Lo
patent: 6044087 (2000-03-01), Muller et al.
patent: 6061362 (2000-05-01), Muller et al.
patent: 6076115 (2000-06-01), Sambamurthy et al.
IEEE Standard 802.3u, 1995, Chapter 22 (pp. 27-80).*
IEEE Standard 802.3u, 1995, Chapter 22 (pp. 27-80).
Preliminary Data Sheet, 8501/8502 Ethernet MII to AUI Interface Adapter, Seeq Technology, INc. Jul. 14, 1997, pp. 1-56.
Lucas Mark C.
McLaughlin Eric
Warling Christian
Hewlett--Packard Company
Ton Anthony
Ton Dang
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