Mechanism to accelerate counter testing without loss of fault co

Details Mechanism to accelerate counter testing without loss of fault co Mechanism to accelerate counter testing without loss of fault co

1993-10-08

1995-03-28

Wambach, Margaret Rose

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Identifying or correcting improper counter operation

377 33, H03K 2140

Patent

active

054024587

ABSTRACT:
Test circuitry for a counter of n number of bits is described. The circuitry includes that which divides the counter into s number of segments when the counter is being tested in a test mode. The invention also includes circuitry for detecting when each segment nears the last count and overriding test mode to reenable a between-segment clock path between the segments before the last count to permit the last count to ripple through the counter to test connections between the segments on the next clock cycle. Previous test implementations did not test the interface between segments because of the prohibitive cost in tester time. In one embodiment, assuming equal numbers of b bits per segment, to fully test a counter using previous techniques, 2.sup.(n-b) +2.sup.b clock cycles would be required. In this technique, only (s-2)+2.sup.b clock cycles are required.

REFERENCES:
patent: 4336448 (1982-06-01), Shipp et al.
IBM Tech Disc. Bul. "Testing Counters" Bodner et al. vol. 18, No. 3 Aug. 1975.

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