Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-06-08
2002-09-17
Sherry, Michael (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB
Reexamination Certificate
active
06452409
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of testing of semiconductor packages, and more particularly, to the holding down of a semiconductor package during testing.
DESCRIPTION OF RELATED ART
Electrical components utilizing integrated circuit chips are used in a number of applications. Controlled Collapsed Chip Connection is an interconnect technology developed as an alternative to wire bonding. This technology is generally known as C4 technology, or flip-chip packaging. Broadly stated, one or more integrated circuit chips are mounted above a single or multiple layer substrate and pads on the chips are electrically connected to corresponding pads on a substrate by plurality of electrical connections, such as solder bumps. The integrated circuit chips may be assembled in an array such as a 10×10 array. The substrate is then electrically connected to another electronic device such as a circuit board with a total package being used in an electronic device such as a computer.
It is desirable to perform an electrical characterization of an integrated circuit by measuring inductance (L), capacitance (C), and resistance (R) at electrical contacts of the integrated circuit. Semiconductor dice, or chips, are typically individually packaged for use in plastic or ceramic packages. This is sometimes referred to as the first level of packaging. The packages required to support, protect, and dissipate heat from the die and to provide a lead system for power and signal distribution to the die. The package is also useful for performing burn-in and functionality testing of the die.
One of the concerns regarding the electrical characterization is the establishment and maintaining of proper contact of the package to a test card through which electrical signals are provided to exercise the package. The measurements of the electrical characteristics of the package will often change if the pressure of the package against the test card changes. Hence, during a single test of a semiconductor package, the electrical characterization may be inaccurate due to changes in pressure of the package against the test card. Furthermore, it is important to provide consistent pressure when comparing the electrical characterization of different semiconductor packages.
During testing, the semiconductor package must normally be held down manually by a test operator during the electrical characterization test. This creates a number of problems, such as inconsistent pressure applied from test to test, fatiguing of the tester who must manually apply pressure against a package, inconsistency of the pressure applied by different human test operators, and mishandling of the package by the human test operators of the package that can result in damage or mismeasurement of the electrical characterization of a package.
SUMMARY OF THE INVENTION
There is a need for an arrangement and method that will provide consistent controlled pressure against the package during testing of the package, thereby eliminating the need for a human to hold down a package during testing and the attendant disadvantages of manual holding down of the package during testing.
These and other needs are met by embodiments of the present invention which provide a mechanism for pressing down a semiconductor package arrangement with a controlled down force. The mechanism comprises a fulcrum and a pressure bar balance mounted on the fulcrum. A biasing device is arranged to bias a first end of the pressure bar in a first direction around the fulcrum. An adjustment device of the mechanism is arranged to limit movement of the pressure bar in the first direction and control the pressure applied against a semiconductor package arrangement by the first end of the pressure bar.
One of the advantages of the mechanism of the present invention is the biasing of the pressure bar around the fulcrum that produces a down force pressure against a semiconductor package arrangement. At the same time, however, the down force provided by the biasing device is limited so that the pressure applied against the semiconductor package arrangement is controlled. Also, since the pressure bar is biased, the first end of the pressure bar may be left against the semiconductor package arrangement in a stable position, relieving a human tester from manually pressing the semiconductor package against a test card.
The earlier stated needs are also met by another embodiment of the present invention which provides a method of testing an integrated circuit package comprising the steps of positioning an integrated circuit package on a test surface and applying a controlled pressure with a pressure bar against the integrated circuit package to hold the integrated circuit package against the test surface. Testing of the integrated circuit package is performed while the controlled pressure is applied against the integrated circuit package by the pressure bar.
Although the present invention has been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the scope of the present invention being limited only by the terms of the appended claims.
REFERENCES:
patent: 4432538 (1984-02-01), Sequin
patent: 4500081 (1985-02-01), Carossino
patent: 4590788 (1986-05-01), Wallis
patent: 5516087 (1996-05-01), Schmid et al.
patent: 6032356 (2000-03-01), Eldridge et al.
patent: 6111420 (2000-08-01), Kelley et al.
Advanced Micro Devices , Inc.
Sherry Michael
Tang Minh N.
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