Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...
Reexamination Certificate
2007-01-09
2007-01-09
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate plural instruction...
Reexamination Certificate
active
10761845
ABSTRACT:
An microprocessor apparatus and method are provided for executing native instructions directly from memory. The apparatus includes instruction translation logic and bypass logic. The instruction translation logic retrieves macro instructions provided via an external instruction bus, and translates each of the macro instructions into associated native instructions for execution. If a first form of a first macro instruction is retrieved, the instruction translation logic directs the microprocessor to enable a native bypass mode and indicates such by asserting a first bit within a control register. The bypass logic is coupled to the instruction translation logic. The bypass logic accesses the first bit within the control register to determine if the native bypass mode has been enabled, and detects wrapper macro instructions and, upon detection of the wrapper macro instructions, disables the instruction translation logic, and provides the native instructions for execution by the microprocessor, thereby bypassing the instruction translation logic.
REFERENCES:
patent: 4156900 (1979-05-01), Gruno et al.
patent: 4245302 (1981-01-01), Amdahl
patent: 5148532 (1992-09-01), Narita et al.
patent: 5235686 (1993-08-01), Bosshart
patent: 5396634 (1995-03-01), Zaidi et al.
patent: 5481684 (1996-01-01), Richter et al.
patent: 5581717 (1996-12-01), Boggs et al.
patent: 5638525 (1997-06-01), Hammond et al.
patent: 5685009 (1997-11-01), Blomgren et al.
patent: 5781750 (1998-07-01), Blomgren et al.
patent: 5787241 (1998-07-01), Henry et al.
patent: 5812913 (1998-09-01), Morris et al.
patent: 5832299 (1998-11-01), Wooten
patent: 5898867 (1999-04-01), Getzlaff et al.
patent: 5930490 (1999-07-01), Bartkowiak
patent: 5968162 (1999-10-01), Yard
patent: 6041403 (2000-03-01), Parker et al.
patent: 6243786 (2001-06-01), Huang et al.
patent: 6618801 (2003-09-01), Knebel et al.
patent: 6625759 (2003-09-01), Petsinger et al.
patent: 6643800 (2003-11-01), Safford et al.
patent: 7000094 (2006-02-01), Nevill et al.
Hennessy et al; “Computer Architecture: A Quantitative Approach”. Second Edition. San Francisco, CA; Morgan Kaufmann Publishers, Inc., 1996. pp. 80-82.
Henry G. Glenn
Martin-de-Nicolas Arturo
Parks Terry
Coleman Eric
Huffman James W.
Huffman Richard K.
IP-First LLC
LandOfFree
Mechanism in a microprocessor for executing native... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Mechanism in a microprocessor for executing native..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Mechanism in a microprocessor for executing native... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3815236