Patent
1995-06-07
1998-01-06
Lall, Parshotam S.
39520001, 39520013, 395843, 395849, G06F 15167
Patent
active
057064326
ABSTRACT:
Computer system processing complexes which can operate actually or apparently synchronously and in parallel or asynchronously in a network have a coupling facility for sending and receiving commands, responses, and data. The memory for the central processing complexes (which is accessible to each of the processing elements) is provided with storage for messages and data for coupling over a communication channel interface. Each of a plurality of processing elements (CPC) has data objects used to maintain state information for shared data in the coupling facility storage. The coupling facility can receive both message commands and data, sending data and responses to messages, and sending and receiving secondary messages. The processing element accessible memory provides a state information buffer control information operation memory block for describing the hardware communication environment associated with the computer system mechanism for storage of state information pertaining to a communications buffer residing in said coupling facility storage. The communication channel has a set of address registers. The system employs four new instructions, PREPARE CHANNEL BUFFER, SIGNAL CHANNEL BUFFER, MOVE CHANNEL BUFFER DATA, and TEST CHANNEL BUFFER, to enable a coupling facility control program to directly manipulate the address registers and control the flow of data, commands and responses between the coupling-facility storage and communication channels for the central processing elements. This provides a direct interface between the coupling facility and an intersystem communication channel for the receipt of messages and data and the related receiving functions.
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Elko David Arlen
Goldrian Gottfried Andreas
Goss Steven Neil
Gregg Thomas Anthony
Helffrich Audrey Ann
Ehrlich Marc A.
International Business Machines - Corporation
Lall Parshotam S.
Winder Patrice L.
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