Mechanism for queuing store data and method therefor

Electrical computers and digital processing systems: processing – Processing architecture

Patent

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710131, 711146, G06F 1200

Patent

active

061675008

ABSTRACT:
A mechanism and method for a store data queue are implemented. Address translation operations for store instructions in a data processor are decoupled from data operations by initiating address translation before source data operands are available. A store data queue snoops the finish buses of execution units for the source operand. A data entry in the data queue that is allocated at dispatch of the store instruction snoops for the source operand required by its corresponding instruction. The data operand is then communicated to a memory device in instruction order thereby simplifying the detection of conflicting stores.

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patent: 5832297 (1998-11-01), Ramagopal
patent: 5930485 (1999-07-01), Kelly
patent: 5974522 (1999-10-01), Torng

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