Electrical computers and digital processing systems: processing – Processing architecture
Patent
1998-08-10
2000-12-26
Coleman, Eric
Electrical computers and digital processing systems: processing
Processing architecture
710131, 711146, G06F 1200
Patent
active
061675008
ABSTRACT:
A mechanism and method for a store data queue are implemented. Address translation operations for store instructions in a data processor are decoupled from data operations by initiating address translation before source data operands are available. A store data queue snoops the finish buses of execution units for the source operand. A data entry in the data queue that is allocated at dispatch of the store instruction snoops for the source operand required by its corresponding instruction. The data operand is then communicated to a memory device in instruction order thereby simplifying the detection of conflicting stores.
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Feiste Kurt Alan
Muhich John Stephen
White Steven Wayne
Coleman Eric
England Anthony V. S.
International Business Machines Corp.
Newberger Barry S.
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