Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – Frequency of cyclic current or voltage
Reexamination Certificate
2001-08-03
2003-04-15
Le, N. (Department: 2858)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
Frequency of cyclic current or voltage
C702S069000, C702S079000, C368S047000, C368S052000, C713S400000, C713S502000
Reexamination Certificate
active
06548997
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to timing circuits and more particularly relates to a mechanism for measuring the time duration of asynchronous events.
BACKGROUND OF THE INVENTION
Numerous applications exist that require the measurement of asynchronous events. A common example is the measurement of timing drift between two clock signals as described in the following example. Many communications systems include both active and standby modes of operation. In the active mode, transmission between the two endpoints (e.g., between a master and a slave) may occur. During the standby mode of operation, however, transmission temporarily ceases between the endpoints.
Standby modes are used to significantly reduce the power consumption of communications devices whereby all but a small portion of necessary circuitry is powered down. Standby modes of operation are used extensively in mobile communications devices, especially those powered by batteries or other limited types of power sources. At some point later in time, the device is ‘awoken’ and returns to the active state for a period of time before entering standby mode again.
A common requirement of communication devices is that while in standby mode the two endpoints need to remain synchronized to a certain extent, such that network timing can be quickly recovered without the need for an extended acquisition phase. Commonly, a device (i.e. typically a portable device based on battery power) switches from a fast clock rate used in the active mode to a lower rate clock while in standby mode, which enables the device to maintain network timing while significantly reducing its power consumption. Since the accuracy, or relative drift, of this slower clock determines the amount of time that the system can remain in standby without actual transmissions being exchanged, it is important to either have an accurate standby clock or to be able to compensate for clock drifts and errors.
In measuring the clock drift of multiple clock signals, the timing of asynchronous events may be required. Often, cascaded flip-flop circuits are used to capture asynchronous events. A common occurrence in these types of circuits is known as the metastability problem wherein one or more flip flops may get confused if the data at the input to the flip flop changes during the setup time interval preceding a clock pulse. The flip flop may make a decision in any case or if the input changed at exactly the wrong time during the moment of decision, such that a decision is not made and the output of the flip flop lingers around the logic threshold for a period of time (i.e. microseconds). In the worst case, the flip-flop settles in a particular state and then switches back to the other state.
Prior art mechanisms intended to reduce the probability of metastability affecting internal logic are based on buffering comprising two or more cascaded synchronized flip-flops, each sampling the output of its predecessor.
Note that in properly designed synchronous systems such problems should not occur as setup times are satisfied by using logic fast enough such that the inputs to flip flops are stable for a period of t
setup
before the next clock pulse. Detecting and measuring asynchronous signals going from one clock domain to another, however, is problematic and may lead to metastability problems because it cannot be guaranteed that input transitions do not occur during the setup time interval.
A schematic diagram illustrating a prior art circuit for measuring the time of asynchronous events is shown in FIG.
1
. The circuit, generally referenced
10
, comprises two flip-flops FF
1
12
, FF
2
14
and a counter
16
. The asynchronous events are input to the circuit by the binary data signal
20
. The events are represented by a low to high transition followed some time later by a high to low transition. A clock signal
18
clocks all three components. The clock rate is assumed to be higher than that of the input data signal.
In operation, the first flip-flop FF
1
synchronizes the asynchronous data signal to the clock. The second flip flop FF
2
acts as a buffer to prevent any metastability of the signal input to the counter. The output of FF
2
enables the counter
16
. After the occurrence of a high to low transition of the data signal, the count value represents the duration between the two events.
A problem in this circuit, however, is that FF
1
may enter metastability since a transition of the asynchronous input data signal may occur within the setup or hold time of FF
1
. In this case, the output of FF
1
cannot be predicted and may oscillate before settling to a random output of
0
or
1
. FF
2
buffers the counter from FF
1
that may be in metastability. This, however, does not guarantee that the counter will be provided the correct enable signal.
A first timing diagram illustrating the inaccuracies of the prior art circuit of
FIG. 1
is shown in FIG.
2
. The data signal representing the asynchronous event is approximately two cycles wide and arrives asynchronously with respect to the clock. Due to FF
2
, the EN signal goes high after a full clock delay. The resultant count represents the length of time between events. Note, however, that the event +/− a whole clock cycle yields the same count result.
A second timing diagram illustrating the inaccuracies of the prior art circuit of
FIG. 1
is shown in FIG.
3
. In this example, the data signal is approximately four clock cycles wide. The resultant count output, however, is again two. Here, the resultant error may be as high as two clock cycles. Thus, the prior art circuit
10
has a resultant resolution of two clocks.
The ‘Base line’ is the ‘calibration period’ measured by the counter after averaging the ambiguity originating from FF
1
/FF
2
. The error incurred is ±½ clock cycle. The overall ‘calibration period’ measurement error is thus ±1 fast clock cycle.
A third timing diagram illustrating the inaccuracies of the prior art circuit of
FIG. 1
is shown in FIG.
4
. The clock
18
is indicated by the fast clock. The data signal, which is four fast clocks wide, is indicated by the slow signal representing the calibration period to be measured. The calibration period in terms of the fast clock is also shown. The resultant counter output is shown. The ambiguity of the slow signal is indicated as +/−½ fast clock, which at the rising and falling edge will yield the same result.
It is important to note that the probability of having a metastable condition on the second flip-flop is highly dependent on the time between the sampling instances at the first stage of the metastability circuit to the sampling at the second stage. In other words, the probability of metastability is inversely proportional to the clock period.
In the case where the sampling of the first stage does not generate a metastability state at its output, the data will be valid at the output of the second stage after the next sampling edge of the second stage. In the case where the first stage sampling does generate a metastability state at its output, there is a probability that by the time the second stage is sampled, the state of the first stage has settled into the state that existed before the sampling.
In this case the data will be valid not after the next sampling edge of the second stage, but after the second sampling edge. This results in an ambiguity as to which edge the data will be valid on at the output of the second stage. The amount of ambiguity is the time difference between the two active sampling edges of the second stage.
In many applications, such as in communication systems (e.g., wired, wireless, portable, etc.), it is desirable to recover and/or measure timing with greater accuracy. There is thus a need for a mechanism for measuring asynchronous events which provides improved accuracy and which reduces the probability of occurrence of metastability conditions in the logic circuitry.
SUMMARY OF THE INVENTION
The present invention provides a novel and u
Bronfer Alexander
Falik Eldad
Brady III Wade J.
Deb Anjan K.
Le N.
Neerings Ronald O.
Telecky , Jr. Frederick J.
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