Mechanism for improving the randomization of cache accesses util

Details Mechanism for improving the randomization of cache accesses util Mechanism for improving the randomization of cache accesses util

1990-10-11

1992-07-21

Lee, Thomas C.

Boots, shoes, and leggings

364224, 3642243, 3642282, 3642387, 3642451, 3642563, 3642551, 3642595, 3642596, 3642599, 364261, 36424341, 3642629, 3642564, 364DIG1, 3642582, 3642598, G06F 7544, G06F 758, G06F 9315, G06F 1210

Patent

active

051330610

ABSTRACT:
An electronic computer system including a central processor and a hierarchical memory system having a large relatively low speed random access system memory and a small high speed set-associative cache memory including a data store section for storing lines of data from the system memory and a cache directory for indicating, by means of line identifier fields at any time, the lines of the system memory data currently resident in cache, is provided with a way to improve the distribution of data across the congruence classes within the cache. A mechanism is provided for performing a permutation operation on an M bit portion (X) of the system memory address, which permutation determines the congruence class into which the address will map. The permutation mechanism performs a bit-matrix multiplication of said M-bit address with an M.times.M matrix (where M is a real positive integer greater than 1) to produce a permuted M-bit address (X'). The directory controls utilize the permuted M-bit address (X') to determine the congruence class of any given memory access and automatically access the congruence class of the permuted address (X') subsequent to the permutation operation to determine if one of the line identifiers which identifies, every member of a congruence class currently stored in the directory, matches an identifier field from the memory access request from the CPU. If the match is successful the data store portion of the cache is accessed at the permuted M-bit address (X') and the requested data line is accessed at the address field specified by the CPU.

REFERENCES:
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patent: 4489378 (1984-12-01), Dixon et al.
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patent: 4775955 (1988-10-01), Liu
L. Liu "XOR Randomization in Cache Congruence Class Indexing" IBM Technical Disclosure Bulletin, vol. 27, No. 2 (Jul. 1984), p. 1097.
Computing Surveys, vol. 14, No. 3, Sep. 1982, pp. 473-530, "Cache Memories" by Alan Jay Smith.

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