Mechanism for implementing one machine cycle executable trap ins

Details Mechanism for implementing one machine cycle executable trap ins Mechanism for implementing one machine cycle executable trap ins

1983-06-30

1986-05-13

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 900

Patent

active

045890650

ABSTRACT:
A mechanism for performing a run-time storage address validity check within one machine cycle. The mechanism, functioning together with an intelligent compiler, eliminates the need for hardware implementation of a storage validity check. More particularly, the mechanism performs its function in one machine cycle in the event that a trap exception does not cause an interrupt. In the rare instance when an interrupt is necessary, a number of machine cycles will be impacted. The mechanism comprises a minimum amount of logic circuitry for determining the trap condition operating in conjunction with conventional, previously existing compare, branch instruction testing, and interrupt generation circuitry.

REFERENCES:
patent: 4074353 (1978-02-01), Woods et al.

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