Mechanism for implementing multiple time-outs

Details Mechanism for implementing multiple time-outs Mechanism for implementing multiple time-outs

1992-05-18

1994-02-15

Heyman, John S.

Excavating

377 15, G06F 1100

Patent

active

052873625

ABSTRACT:
A time-out detector for a computer system to record any number of time-out events with a predetermined period. The time-out detector comprises A-counter coupled to a transmission medium for incrementing in response to an initiating event and decrementing in response to a terminating event; B-counter coupled to the transmission medium for incrementing in response to an initiating event and decrementing in response to a terminating event; I-state bit coupled to the A- and B- counters for toggling between logic 0 and logic 1 states at each prescale pulse, wherein the logic 0 state causes the A-counter to increment by 1 count at each initiating event, and the logic 1 state causes the B-counter to increment by 1 count at each initiating event; T-state bit coupled to the A- and B- counters for toggling between logic 0 and logic 1 states, wherein the logic 0 state causes the A-counter to decrement by 1 at each terminating event, and if the contents of said A-counter is then equal to 0, the T-state bit is set to 1. The logic 1 state causes the B-counter to decrement by 1 at each terminating event, and if the contents of said B-counter is then equal to 0, the T-state bit is reset to 0, such that the A-counter records any number of time-out events when the I-state bit is logic 1 and the B-counter records any number of time-out events when the I-state bit is logic 0.

REFERENCES:
patent: 3795800 (1974-03-01), Nimmo
patent: 4538273 (1985-08-01), Lasser
patent: 4627060 (1986-12-01), Huang et al.
patent: 5014190 (1991-05-01), Johnson
patent: 5233613 (1993-08-01), Allen et al.

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