Mechanism for enforcing the correct order of instruction executi

Details Mechanism for enforcing the correct order of instruction executi Mechanism for enforcing the correct order of instruction executi

1993-06-17

1995-05-30

Coleman, Eric

Boots, shoes, and leggings

395800, 395425, 364DIG1, G06F 930

Patent

active

054209900

ABSTRACT:
An apparatus for enforcing that selected instructions are executed in a correct order, comprising a first content addressable memory for storing load addresses of data read from the memory by the selected instructions. The first content addressable memory comparing the store addresses with the load addresses of data to be written to the memory. The first content addressable memory generating a first signal, if one of the load addresses is identical to a subsequently compared one of the store addresses. The apparatus further including a second content addressable memory for storing and comparing states of the data read and written by the selected instructions. The second content addressable memory generating a second signal, if one of the stored states is identical to one of said compared states. The stored states including a program counter to repeat the execution of the selected instructions upon detecting the first and second signals.

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