Mechanism for enabling an array of numerous large high speed cou

Details Mechanism for enabling an array of numerous large high speed cou Mechanism for enabling an array of numerous large high speed cou

1997-04-14

1998-08-04

Wambach, Margaret Rose

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Using shift register

377 16, 377 73, G11C 1900

Patent

active

057906254

ABSTRACT:
A large number of frequent events may be accurately counted by employing a shift register. The values of several bit positions within the shift register are logically combined to generate an input to the shift register. The input is shifted in to alter the register contents whenever an event to be counted occurs. The bit positions for generating the input are selected to produce the longest sequence of nonrepeating patterns possible. The event counter may be implemented in a small area, allowing a large number of event counters to be implemented in an array like structure within a single device and to operate as extremely high frequencies.

REFERENCES:
patent: 5581228 (1996-12-01), Cadieux et al.
patent: 5740220 (1998-04-01), Zandveld

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