Mechanism for dynamically determining and distributing computer

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364270, 364271, 3642711, 364DIG1, G06F 104

Patent

active

055727182

ABSTRACT:
A computer includes a mother board having a clock A thereon that provides a primary clock to a clock distribution buffer that distributes the clock that drives it to clock electronic components on the mother board. The mother board has a socket for receiving an optional module having a clock B thereon. A clock switching circuit is connected to the clock A and to the clock B socket terminus. An edge detector connected to clock B detects an edge of the clock B. A detection window indicator is asserted upon a predetermined condition, such as that power is on and stable. A control circuit, connected to the clock switching circuit, to the edge detector and to the detection window indicator causes the secondary clock to be selected and substituted for the primary clock.

REFERENCES:
patent: 5305452 (1994-04-01), Khan et al.
patent: 5448715 (1995-09-01), Lelm et al.
patent: 5450574 (1995-09-01), Madter et al.
patent: 5450958 (1995-09-01), Price et al.
patent: 5455927 (1995-10-01), Huang

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