Mechanism for comparing two registers and storing the result in

Details Mechanism for comparing two registers and storing the result in Mechanism for comparing two registers and storing the result in

1985-06-28

1988-05-24

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 922

Patent

active

047470461

ABSTRACT:
In a computer device, an instruction set which uses a two-instruction sequence to store the result of a comparison is provided. The two-instruction sequence, which uses no branch instructions, does not need to wait for condition resolution before storing conditional results. Additionally, it also is capable of implementing slightly more general operations than simply storing a zero or one value of a comparison. Basically, the instruction set in accordance with the invention compares two operands and unconditionally stores a zero, which represents a Boolean "false", into a selected destination. The instruction set then conditionally nullifies the instruction following it, thus effecting a highly efficient execution of a sequence of instructions compared to the prior art.

REFERENCES:
patent: 4569016 (1986-02-01), Hao et al.
patent: 4589065 (1986-05-01), Auslander et al.
Patterson, D. A. and Sequin C. H., "A VLSI RISC", Computer, Sep. 1982, pp. 8-21.

Affiliated with

Also associated with

Rating

Mechanism for comparing two registers and storing the result in does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Mechanism for comparing two registers and storing the result in , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Mechanism for comparing two registers and storing the result in will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1062505