Computer graphics processing and selective visual display system – Computer graphics processing – Attributes
Reexamination Certificate
2000-05-05
2004-09-14
Razavi, Michael (Department: 2672)
Computer graphics processing and selective visual display system
Computer graphics processing
Attributes
C345S605000
Reexamination Certificate
active
06791564
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to computer processors and, more specifically, to a mechanism for clipping RGB values to at most an acceptable maximum during integer transfer.
BACKGROUND OF THE INVENTION
Modern computer systems use a number of different processor architectures to execute software programs. In conventional microprocessor-based systems, a computer program is made up of a number of macro instructions that are provided to the microprocessor for execution. The microprocessor decodes each macro instruction into a sequence of micro instructions, i.e., more elemental machine instructions that the microprocessor is capable of executing individually, and executes the micro instructions in the sequence.
Most processors include a floating-point unit (FPU) to assist in the processing of numbers expressed in floating-point form (mantissa and exponent). Such numbers are often encountered in complex numerical analyses that the processor may be called upon to perform. Because an FPU is specially adapted to process such numbers, it serves to make the microprocessor faster overall. FPUs for microprocessors were originally introduced as a part of a math coprocessor that operated in tandem with the microprocessor. Now, FPUs are often incorporated into microprocessors.
FPUs are frequently called upon to make repetitive calculations. One important calculation is determining color values that are to be displayed on a monitor.
Colors are commonly represented by three independent values. With so-called “RGB” monitors, one value represents red, another green and yet another blue. With various concentrations of these three primary colors, one can in theory create any hue in the spectrum of visible light.
However, since a computer only uses a finite set of values for each of these three colors, only a finite set of colors can be produced. For example, an EGA, one of the earlier graphics adapters that could produce RGB color, employed two bits each for red, green and blue. Therefore, red, green and blue could each take four values, giving a maximum of 64 colors. Most standard computers today represent red, green and blue in eight bits yielding 256 possible intensity levels. Therefore, approximately 16 million colors can be created with different combinations of red, green and blue intensity.
The values of these colors may be determined by either hardware or software. Sometimes, the numbers initially used to represent color values are expressed as floating-point numbers. However, a conversion to 8-bit integer form should take place before the colors represented by these values can be displayed.
To perform this conversion, prior art microprocessors employed two separate microcode-based clipping functions to convert each value. The clipping functions operated thus: if the color value was too high (over 255, when an 8-bit integer result is desired), the register corresponding to that color and position was set to 255. If the value was too low (below 0), the register was set to 0.
The FPU might use microcode, such as the following, to accomplish this clipping:
If (Red)>255 Red==255
If (Red)< Red==0
Therefore, the FPU was required to execute two separate inequality operations when faced with inappropriate values for the colors of course, each of these inequality operations requires processor time.
The number of times the FPU performs these calculations is such that any savings in time in performing these steps of the calculations would be advantageous. Accordingly, what is needed in the art is a mechanism that can perform an RGB clipping function with greater efficiency.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a mechanism for, and method of, clipping an RGB integer value to an n-bit maximum value and a processor incorporating the mechanism or the method. In one embodiment, the mechanism includes: (1) a multiplexer having a first input that accepts n low-order bits of the RGB integer value and a select input that accepts at least one high-order bit of the RGB integer value and (2) an n-bit maximum value generator, coupled to a second input of the multiplexer, that provides the n-bit maximum value to the second input, an output of the multiplexer providing the n low-order bits when the at least one high order bit has a zero value and providing the n-bit maximum value when the at least one high order bit has a nonzero value.
The present invention therefore introduces the broad concept of employing highbit-select logic to perform RGB value-clipping in hardware, rather than by separate software instruction.
In one embodiment of the present invention, n equals eight. This means that the n-bit maximum value is 255, which is a standard maximum RGB value. Of course, the present invention is not limited to a particular value for n.
In one embodiment of the present invention, the select input accepts eight low-order bits of the RGB integer value. Again, this corresponds to a value of at most 255. In an embodiment to be illustrated and described, all of the remaining (high-order) bits are provided to the select input. In the case of a 16-bit incoming RGB integer value, the lower 8 bits are accepted into the first input and the upper 8 bits are accepted into the select input. Of course, this need not be the case.
In one embodiment of the present invention, the multiplexer accepts the RGB integer value from a floating-point register. In two embodiments to be illustrated and described, the floating-point register contains the RGB value in 16-bit integer form. Alternatively, the incoming RGB integer value can be accepted from an integer register.
In one embodiment of the present invention, the output is coupled to an n-bit integer register. If n equals 8, then the register is, but is not required to be, 8 bits wide.
In one embodiment of the present invention, the n-bit maximum value generator comprises a voltage source coupled to the second input. In an embodiment to be illustrated and described, all of the lines of the second input are set to a logical one, thereby generating the n-bit maximum value (255 in the embodiment to be illustrated and described).
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
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patent
Elliott Timothy A.
Henry G. Glenn
Harrison Chante
Hitt David
Huffman James W.
IP-First LLC
Razavi Michael
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