Pulse or digital communications – Transceivers – Transmission interface between two stations or terminals
Reexamination Certificate
1999-01-20
2003-01-14
Pham, Chi (Department: 2631)
Pulse or digital communications
Transceivers
Transmission interface between two stations or terminals
C710S260000
Reexamination Certificate
active
06507609
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to data networks, and more particularly, to an interrupt management system that handles interrupt signals produced in different clock domains.
BACKGROUND ART
The growth in computer applications that require heavy data traffic and the increasing availability of high-speed transmission lines and intelligent communication switches create a need for computer systems able to manage a huge amount of data at high rates. For example, high-speed communication networks may require a central processing unit (CPU) to be interrupted at rates of 20,000-100,000 interrupts per second in response to hundreds various events.
In a network controller chip, interrupt request signals to an external CPU may be produced to direct the CPU's attention to such events as a user intervention, system and memory errors, missed frames, reception and transmission operations, management operations, etc. Interrupt events may be originated in various portions of the controller. However, separate clocks may control operations in different portions of the controller. As a result, different interrupt events may be represented by interrupt signals of different duration.
An interrupt management block produces interrupt request signals supplied to an external CPU when an interrupt event occurs. As a local clock different from clocks associated with interrupt events may control the interrupt management unit, it would be desirable to provide a mechanism for capturing and reporting interrupt events of different clock domains.
DISCLOSURE OF THE INVENTION
Accordingly, a primary object of the present invention is to provide an interrupt management block able to capture and report interrupt events originated in network controller sections controlled by different clocks.
The above and other advantages of the invention are achieved, at least in part, by providing an interrupt management circuit that comprises an interrupt event detector for receiving an interrupt event signal representing an interrupt event that may occur in different units controlled by separate independent local clocks. An interrupt synchronizing signal produced by the interrupt event detector is used by an edge detector for generating an interrupt edge signal having a duration equal to a predetermined number of periods of a local clock signal that controls the interrupt management circuit. An interrupt read circuit is responsive to a read signal from the host for storing interrupt event data represented by the interrupt edge signal. An interrupt register is responsive to the interrupt event data transferred from the interrupt read circuit for producing interrupt request bits sent to the host.
In accordance with a first aspect of the invention, duration of the interrupt event signal may correspond to a time period during which the event represented by the interrupt event signal occurs. The interrupt event signal may have variable duration.
In accordance with a preferred embodiment of the present invention, the interrupt event detector may comprise a first flip-flop for receiving the interrupt event signal, and a second flip-flop coupled to the first flip-flop for producing the interrupt synchronizing signal. Also, the interrupt event detector may comprise a first OR gate having a first input coupled to an output of the first flip-flop, a second input coupled to an output of the second flip-flop, and an output connected to a data input of the first flip-flop. The interrupt event signal may be supplied to a reset input of the first flip-flop.
The edge detector may be adapted to produce the interrupt edge signal having an edge that coincides in time with an edge of the interrupt synchronizing signal, and duration equal to three periods of the local clock signal. The edge detector may comprise third, fourth and fifth flip-flops, and a second OR gate having a first input coupled to an output of the second flip-flop, a second input coupled to an output of the third flip-flop, and a third input connected to an output of the fourth flip-flop. Also, the edge detector may comprise a gate responsive to outputs of the second OR gate and the fifth flip-flop for producing the interrupt edge signal.
The interrupt read circuit may comprise a sixth flip-flop and a third OR gate having a first input coupled to an output of the sixth flip-flop and a second input supplied with the interrupt edge signal. A first multiplexer controlled by the read signal may be coupled between an output of the third OR gate and input of the sixth flip-flop. A second multiplexer may be coupled between the output of the OR gate and an input of the first multiplexer. The second multiplexer may be controlled by a read reset signal for resetting contents of the sixth flip-flop.
The interrupt register may comprise a seventh flip-flop for producing the interrupt request bits, and a third multiplexer having a first input connected to an output of the seventh flip-flop and a second input coupled to an output of the sixth flip-flop. The third multiplexer may be controlled by the read signal for maintaining the contents of the seventh flip-flop unchanged during an interrupt request read operation.
In accordance with another aspect of the invention, a data communication network comprises a host and a network adapter coupled to the host via a PCI bus. The network adapter has an interrupt capture and storage mechanism responsive to interrupt events of variable duration for producing an interrupt request signals transferred to the PCI bus to report the events to the host.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
REFERENCES:
patent: 5384906 (1995-01-01), Horst
patent: 5708814 (1998-01-01), Short et al.
patent: 5708817 (1998-01-01), Ng et al.
patent: 6115779 (2000-09-01), Haubursin et al.
Pham Chi
Tran Khai
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