Mechanism for automatically determining ISDN channel...

Details Mechanism for automatically determining ISDN channel... Mechanism for automatically determining ISDN channel...

1998-03-10

2002-03-12

Olms, Douglas (Department: 2661)

Multiplex communications

Channel assignment techniques

Combining or distributing information via time channels...

C370S463000, C370S524000

Reexamination Certificate

active

06356556

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates in general to communication networks, and is particularly directed to a mechanism for automatically determining the channel availability and DS0 time slot transmission assignment order of bearer and data channels that may be employed by ISDN interface circuit cards, such as U-Basic Rate-One Transmission Extension, or U-BRITE, ISDN circuit cards (also known in the industry as Basic Rate Interface Transmission Extension (U-BRITE) cards), for transporting a plurality of digital subscriber line (DSL) channels between geographically separated sites where ISDN channe-linterfacing channel banks are installed.
BACKGROUND OF THE INVENTION
Integrated services digital network (ISDN) communication systems enable telephone service providers to supply multiple types of signalling channels from a central office to a network termination interface at a customer premises site. An example of a reduced complexity ‘extended distance’ ISDN communication network architecture is diagrammatically illustrated in
FIG. 1
as comprising a PCM communication link (such as a T1 data rate (1.544 Mb/s) optical fiber link)
10
, through which a channel bank
20
at a ‘west’ end of the PCM link
10
transmits and receives signalling traffic with respect to a customer premises equipment (CPE) served by a channel bank
30
at a remote or ‘east’ end of the PCM link
10
. The channel bank
20
at the west end is coupled by way of a link
25
to a central office switch
21
(such as a 5ESS switch manufactured by AT&T), and includes a line interface unit (LIU)
21
that is coupled to the PCM link
10
. The channel bank
30
at the east end has an LIU coupled to the PCM link
10
and is coupled by way of a local loop
35
to a customer premises
40
.
As shown in
FIG. 2
, in order to provide service to remote customers at customer premise sites
40
, the channel bank
30
at the east end of the PCM link
10
has a plurality of U-BRITE circuit cards
33
installed in the channel bank unit's backplane
34
. Each respective U-BRITE circuit card
33
is dedicated to providing extended ISDN service to remote customer premises equipment via a local loop
35
, between the U-BRITE circuit card and digital communication equipment
40
installed at a respective customer premises.
A carrier system transceiver within a line interface unit (LIU) is operative, under control of an attendant communications control processor to transmit and receive standard 2B+D ISDN data traffic over the PCM digital data link
10
. To interface digital subscriber loop (DSL) over the local loop (twisted pair)
35
to the customer premises equipment (CPE)
40
, the U-BRITE circuit card
33
also includes a line transceiver and an associated line interface, which are also operative, under internal microprocessor control, to interface PCM data with the line interface unit
31
and to transmit and receive (basic rate 2B1Q) ISDN signals over the local loop
35
to and from CPE
40
.
For transporting basic rate (2B+D) ISDN channels, the communications industry standard TR-TSY-000397 multiplexing format of a respective DSL channel conveyed by the T1 link is a DS0 byte triplet, accommodating a pair of bearer channel time slot octets B
1
and B
2
and a data channel time slot octet D. As diagrammatically illustrated in
FIG. 3
, within a respective DSL time slot, these three DS0 channel octets are typically ordered such that the bearer octet B
1
is transmitted first, followed by the data octet D and then the second bearer octet B
2
, although the order may change depending upon the equipment vendor.
For example, some vendor's cards switch the order of the second and third octets, such that the data channel octet D immediately follows the second bearer channel octet B
2
, which immediately follows the first transmitted bearer channel octet B
1
, as shown in FIG.
4
. Other vendor's cards switch the order of the first and second octets, such that the data channel octet D immediately precedes follows the first bearer channel octet B
1
, which immediately precedes the second bearer channel octet B
2
, as shown in FIG.
5
. Regardless of the multiplexing order chosen, it is customary industry practice that the B
1
channel is assigned a DS0 time slot ahead of that of the B
2
bearer channel. Namely, the B
2
channel, if used, will follow either directly after the D channel (as shown in FIG.
3
), or after the B
1
channel (as shown in FIGS.
4
and
5
).
Regardless of the multiplexing order chosen, whether or not a respective DS0 octet/channel is enabled within a particular DSL time slot is customarily defined by manually presetting each of a set of three option switches—one for each channel (B
1
, B
2
and D)—on the ISDN interface card. As a consequence, a not infrequent problem faced by a telecommunication service provider is the failure of an installer to have properly set the DS0 option switches on one or more ISDN interface (e.g., U-BRITE) cards in accordance with their intended ISDN channel assignments. Namely, unless the DS0 octet time slot assignment switches are properly optioned, then when the ISDN interface cards attempt to communicate with one another by way of a respective DSL time slot, they may encounter different DS0 time slot octet assignments, resulting in a lack of DS0 multiplexing synchronization between the two cards and transmission failure. A conventional solution to this problem, which is both labor intensive and time consuming, has been to dispatch a service technician to the remote site to physically examine and manually change the DS0 time slot option switch settings.
SUMMARY OF THE INVENTION
In accordance with the present invention, this conventional ‘travelling technician’ approach to solving the above-described DS0 time slot misconfiguration problem is successfully remedied by a software-based DS0 channel multiplexing format analysis routine exercised by the ISDN interface card's microcontroller, so as to automatically determine what DS0 channels are available at the remote ISDN circuit card and the order in which those DS0 channels are multiplexed by that remote card's circuitry.
For this purpose, the DS0 time slot monitoring routine of the present invention initially supplies a continuous stream of ‘one’
0
bits as data to be transmitted to each of the three available DS0 channels of the DSL time slot of interest, so that an error detection mechanism employed by the ISDN card, such as a cyclic redundancy check (CRC) mechanism, operating on each data stream will cause an ‘all ones’ associated code to be transmitted in the D octet portion of a respective DSL time slot of interest to a far end card that is potentially installed in the backplane card slot associated with the DSL time slot of interest.
A given assumption is that, if a remote ISDN card is installed for a DSL time slot of interest, at least one bearer channel—the B
1
channel if only one bearer channel is used and the D channel will be enabled for that DSL time slot. The multiplexing order of the DS0 time slots may be initially established at a prescribed default order, such as B
1
-D-B
2
, as shown in
FIG. 3
, described above.
For this initial default order, the contents of the returned DSL time slot of interest are monitored to determine whether the second DS0 time slot contains the CRC data expected to be returned over the D channel from the far end card. If so, it is concluded that the second DS0 time slot is also used for D channel signalling by the far end card. The routine then proceeds to determine whether or not the second bearer channel B
2
is enabled.
For this purpose, the all one's data previously asserted for the second bearer channel B
2
is replaced with a prescribed (not all one's) data sequence, which causes the CRC operator in the transmitting card to compute a CRC code different from that for the original all one's sequence. This CRC code is then transmitted over the D channel to the far end circuit. The receiver at the far end card recalculates its

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