Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2004-02-20
2009-11-10
Rodriguez, Paul L (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C714S741000, C717S124000, C716S030000
Reexamination Certificate
active
07617084
ABSTRACT:
Disclosed is a method, mechanism, and computer usable medium for simultaneous processing or debugging of multiple programming languages. A particularly disclosed approach provides a method and mechanism for resolving the issue of simultaneous debugging of hardware represented by an HDL, e.g., Verilog or VHDL, and software, e.g., represented by C, C++, SystemC code. This approach overcomes the problem of the HDL portion of the design being inaccessible when C, C++ or SystemC code is debugged.
REFERENCES:
patent: 5911059 (1999-06-01), Profit, Jr.
patent: 6182258 (2001-01-01), Hollander
patent: 6188975 (2001-02-01), Gay
patent: 6226780 (2001-05-01), Bahra et al.
patent: 6263303 (2001-07-01), Yu et al.
patent: 6466898 (2002-10-01), Chan
patent: 6581191 (2003-06-01), Schubert et al.
patent: 6587995 (2003-07-01), Duboc et al.
patent: 7017097 (2006-03-01), Moore et al.
patent: 7035781 (2006-04-01), Flake et al.
patent: 7058562 (2006-06-01), Powell
patent: 7117139 (2006-10-01), Bian
patent: 7146300 (2006-12-01), Zammit et al.
patent: 7464373 (2008-12-01), Yunt et al.
Martinolle et al, “A Procedural Language Interface for VHDL”, Proceedings of the Verilog HDL Conference and VHDL International Users Forum, 1998, pp. 32-38.
McKinney, Michael, “Integrating Perl, Tcl and C++ into Simulation-Based ASIC Verification Environments”, Proceedings of the 6th IEEE International High-Level Design Validation and Test Workshop, 2001, pp. 19-24.
Bombana et al, “SystemC-VHDL Co-Simulation and Synthesis in the HW Domain”, Design, Automation and Test in Europe Conference and Exhibition, 2003, pp. 101-105.
Benini et al, “SystemC Cosimulation and Emulation of Multiprocessor SoC Designs”, IEEE Computer Society, Apr. 2003, pp. 53-59.
Gailser Research , “TSIM Simulator User's Manual”, Version 1.2, Jun. 2003, sections 1, 3 (best available copy, obtained from Google Scholar, html version of www.orbitabluebox.com/pdf/english/tsim-1.2.pdf+).
Stallman et al, “Debugging with GDB: The GNU Source-Level Debugger”, Jan. 2002, book summary, obtained on www.gnu.org.
Guerra et al, “Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification”, DAC '99, New Orleans, LA, 1999.
Olcoz et al, “VHDL Virtual Prototyping” Proceedings of the 6th IEEE International Workshop on Rapid System Prototyping, Jun. 7-9, 1995, pp. 161-167.
Fummi et al, “Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC”, Proceedings of Design, Automation and Test in Europe Conference and Exhibition, Feb. 16-20, 2004, vol. 1, pp. 564-569.
Martionelle et al, “Mixed Language Design Data Access: Procedural Interface Design Considerations”, Proceedings of the 2000 VHDL International Users Forum Fall Workshop, Oct. 18-20, 2000, pp. 95-99.
Bian et al , “VIDE: A Visual VHDL Integrated Design Environment”, Proceedings of the ASP-DAC'97, Jan. 28-31, 1997, pp. 383-386.
Martionelle et al, “Mixed Language Design Data Access: Procedural Interface Design Considerations”, VHDL International Users Forum Fall Workshop, 2000, Proceedings, Oct. 18-20, 2000, pp. 95-99.
Damasevicius, R. et al. “Separation of Concerns in Multi-Language Specifications” Informatica, 2002, vol. 13, No. 3, pp. 1-20.
Jerraya, A. et al. “Multi-Language System Design” Proceedings of the 1999 Design, Automation and Test in Europe Conference and Exhibition, Munich, Germany, Mar. 9-12, 1999, pp. 696-699.
Kleinjohann, B. “Multilanguage Design” Proceedings of the International Federation for Information Processing (IFIP) WG 10.3/WG 10.5, 1998, 14 pgs.
Mahajan, R. et al. “A Multi-Language Goal-Tree Based Functional Test Planning System” Proceedings of the 2002 International Test Conference. Oct. 7-10, 2002, pp. 472-481.
Mills, M. et al, “Hardware/Software Co-design: VHDL and Ada 95 Code Migration and Integrated Analysis” Proceedings of the 1998 Annual ACM SIGAda International Conference on Ada, Washington, DC, 1998, pp. 18-27.
Harris Mark
Koslow Douglas J.
Valencia Leonardo
Cadence Design Systems Inc.
Jacob Mary C
Rodriguez Paul L
Vista IP Law Group LLP
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