Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated – With specified filler material
Reexamination Certificate
2001-10-24
2004-08-17
Nadav, Ori (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Encapsulated
With specified filler material
C257S692000, C257S724000, C257S789000
Reexamination Certificate
active
06777818
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to electronics packaging. More particularly, the present invention relates to an electronic package that includes a die packaged on a thin interposer, and to manufacturing methods related thereto.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs) have typically been assembled into electronic packages by physically and electrically coupling them to a substrate made of organic or ceramic material. One or more such IC packages can be physically and electrically coupled to a secondary substrate such as a printed circuit board (PCB) or motherboard to form an electronic assembly. The electronic assembly can be part of an electronic system. An electronic system is broadly defined herein as any product comprising an electronic assembly. Examples of electronic systems include computers (e.g., desktop, laptop, hand-held, server, etc.), wireless communications devices (e.g., cellular phones, cordless phones, pagers, etc.), computer-related peripherals (e.g., printers, scanners, monitors, etc.), entertainment devices (e.g., televisions, radios, stereos, tape and compact disc players, video cassette recorders, MP3 (Motion Picture Experts Group, Audio Layer 3) players, etc.), and the like.
Manufacturers of electronic systems constantly try to improve product performance while reducing production costs. This is particularly true regarding the packaging of ICs, where each new generation of packaging must provide increased performance while generally being smaller or more compact in size. Therefore, manufacturers of high-end ICs, such as processors, continually develop IC packages that are thinner, lighter-weight, and/or more resilient because such packaging is useful for many applications.
A typical package includes an IC, such as a die, that is mounted on an interposer which functionally connects the die through a hierarchy of electrically conductive paths to the other elements, such as other ICs, that make up the electronic system. Surface mount technology (SMT) is a widely known technique for coupling a die to an interposer. One of the conventional methods for surface-mounting an IC on an interposer is called “controlled collapse chip connect” (C4). In fabricating a C4 joint, the electrically conductive terminals or lands of an IC component are soldered directly to corresponding lands on the surface of the interposer using reflowable solder bumps or balls. The C4 process is widely used because of its robustness and simplicity.
The C4 joints are often used in combination with an underfill, such as an epoxy. The epoxy helps to hold the joint together when there is thermal expansion and contraction of the package during operation of the integrated circuit.
Power delivery is an area of microprocessor development that will be crucial to improving future microprocessors. One of the major limitations associated with power delivery is the inductive path, or loop, between a die and one or more capacitors that provide power to the components in the die before another source, such as a voltage regulator, is able to provide a steady supply of power. This limitation is typically addressed by attaching the capacitors to the underside of a thin interposer that is positioned between the die and the capacitors in order to minimize the distance between the die and the capacitors. Reducing the distance between the capacitors and the die minimizes the inductive loop that is generated when supplying a voltage to the die. However, the thin interposer leads to another problem as the thin interposer is unable to handle the mechanical loads that are applied by the heat sinks which are typically used to cool the integrated circuit.
FIGS. 1 and 2
show two different types of prior art packages. The package
10
illustrated in
FIG. 1
includes a die
12
that is mounted onto an interposer
14
using a conventional C4 joint that is supplemented by a conventional underfill
15
. A pin carrier
16
is attached to the underside of the interposer
14
to support the interposer
14
along at least the entire area of the die
12
. The design of the package
10
, in particular the pin carrier
16
, does not permit capacitors, or any other electronic component, to be mounted to the underside of the interposer
14
in that area of the interposer which is opposite to the die
12
. Therefore, the prior art package
10
shown in
FIG. 1
suffers from an inductive path problem.
FIG. 2
shows a prior art package
20
that overcomes the inductive path problem. The package
20
includes a die
22
that is mounted onto a thin interposer
24
. The die
22
is similarly mounted to the interposer
24
using a conventional C4 joint that is supplemented by a conventional underfill
25
. A pin carrier
26
that includes a cavity
27
is mounted to the underside of the thin interposer
24
. The cavity
27
in the pin carrier
26
is positioned underneath the die
22
such that capacitors
28
may be mounted to the underside of the interposer
24
opposite to the die
22
using conventional surface mount technology. Placing the capacitors
28
against the interposer
24
within the cavity
27
of the pin carrier
26
reduces the distance between the die
22
and capacitors
28
. This reduced distance minimizes the inductive loop problem. However, the thin interposer
24
is incapable of withstanding the mechanical load that is applied to the package
20
by heat sinks and other thermal elements within the integrated circuit during operation of the electronic system where the package
20
is located. The mechanical load generates package deflection that results in multiple failure modes, including internal damage to the package circuitry and/or damage to the capacitor joints.
As the internal circuitry of processors operates at higher and higher clock frequencies, and as processors operate at higher and higher power levels, the amount of loop inductance produced within processor packages often increases to unacceptable levels. Therefore, there is a significant need for a reliable electronics package, and methods of fabricating an electronics package, that generates minimal loop inductance within the package yet is mechanically stable.
REFERENCES:
patent: 5570274 (1996-10-01), Saito et al.
patent: 6400033 (2002-06-01), Darveaux
patent: 6452113 (2002-09-01), Dibene, II et al.
Nadav Ori
Schwegman Lundberg Woessner & Kluth P.A.
LandOfFree
Mechanical support system for a thin package does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Mechanical support system for a thin package, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Mechanical support system for a thin package will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3291626