Abrading – Abrading process – Glass or stone abrading
Reexamination Certificate
2003-04-09
2004-05-25
Hail, III, Joseph J. (Department: 3723)
Abrading
Abrading process
Glass or stone abrading
C451S036000, C451S041000, C451S037000, C451S060000, C451S285000, C451S287000, C451S446000, C451S908000, C438S622000, C438S631000, C438S633000, C438S647000, C438S648000
Reexamination Certificate
active
06739953
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to methods for performing polishing of semiconductor wafers. More particularly, the present invention relates to methods for mechanical stress free processing of damascene interconnects on semiconductor wafers during the manufacture of semiconductor integrated circuits.
2. Description of the Related Art
As integrated circuits become smaller, it becomes more desirable to reduce interconnection delays through the selection of materials used in the interconnects and associated dielectric layers. The propagation delays through the interconnects are proportional to the resistance of the interconnects and the capacitance offered by the dielectric. In fact, as integrated devices become smaller, the resistance capacitance (RC) delay time of signal propagation along interconnects becomes the dominant factor limiting overall chip speed. In order to improve the interconnect performance, higher conductance and lower capacitance is required of the interconnects. In order to accommodate these objectives, the trend has been towards the use of copper for interconnects and damascene methods for forming the interconnects.
For conductors, copper has gained favor in the industry because of its many advantages, including its low resistance. In such processes, conducting metal (e.g., copper) is inlaid into trench and via structures of insulating material (e.g., low-k dielectric materials). CMP (Chemical Mechanical Polishing) is used to remove conducting metal (e.g., copper) in single or dual damascene processes. With the advent of copper technology, resistance has been minimized and attention has been focused on reducing capacitance.
One method conventionally used to reduce capacitance is to reduce the average dielectric constant k of the thin insulating films surrounding interconnects through the introduction of porosity. The dielectric layers in conventional integrated circuits have traditionally been formed of SiO
2
, which has a dielectric constant of about 4.0. A number of dielectric materials have been developed having a dielectric constant lower than that of SiO
2
. These are generally referred to as low-k materials.
Integrated circuits are often made up of many interconnect levels to connect the various devices of the circuit. Low-k dielectric materials are used to electrically isolate the different levels of metallization. Thus, a semiconductor device may include several low-k layers disposed on top of each other.
But low-k materials used in interconnect dielectrics exhibit low mechanical strength. That is, the lack of mechanical rigidity of the composite low-k and metal interconnect materials causes delamination of the low-k to low-k layers and low-k to copper layers when shear forces are applied. The mechanical strength of low-k films is considerably less than that of traditional silicon dioxide. As the dielectric constants reach lower values, the structural integrity of the films decrease. This compromised mechanical strength of the low-k film significantly increases the likelihood of damage to the structure of the low-k copper dual damascene system during conventional chemical mechanical polishing (CMP). That is, while the wafers are subjected to chemical mechanical polishing (CMP), shear stresses and other mechanical damage may cause defects that render the devices useless.
This presents an ever-challenging task for CMP and developers of dielectric films. For example, CMP vendors are working on new pad materials and slurry solutions to optimize planarization with a much lower down force, but this approach has its limitations. But a reduction in down force will cause a major reduction in the removal rate of the copper.
Thus, the poor mechanical strength of the low-k material affects the ability to use chemical mechanical polishing to remove the copper film and planarize the wafer surface between copper layers.
Accordingly, it is desirable to provide improved methods of planarizing semiconductor wafer surfaces to minimize or eliminate damage to dielectric layers. In particular, it is desirable to provide more effective methods of planarizing surfaces in low-k damascene interconnect structures to avoid defects caused by shear stresses or other damage from conventional CMP procedures.
SUMMARY OF THE INVENTION
To achieve the foregoing, the present invention provides methods for processing semiconductor wafers using a combination of chemical mechanical polishing (CMP) and electropolishing. The processing sequence involves an initial light mechanical polish to planarize the copper metal layer followed by an electropolishing of the copper layer. The electropolishing proceeds until the copper layer is removed sufficiently to expose the barrier metal layer. The same electrolyte/slurry is used for both steps, the steps being distinguished by changing the down force applied to the wafer and the voltage applied across the polishing head and platen.
By processing the semiconductor wafer in this manner, a non-contact method of removing copper from the wafer is provided.
With these techniques, a copper damascene structure may be planarized and the excess metal removed by using the polishing head and platen as the respective anode and cathode for electropolishing. In this configuration, the polishing pad is conductive and acts as a pseudo polishing pad during the electropolishing. An electrolytic solution is maintained as a barrier layer on the polishing pad by suitably controlling the viscosity of the electrolytic slurry dispensed on the polishing pad, such as by controlling the temperature and additive concentration for the slurry.
According to one embodiment, a method of planarizing of a surface of a semiconductor substrate is provided. A copper layer is inlaid in a dielectric layer of the substrate. The semiconductor substrate is disposed opposite to a polishing pad and relative movement provided between the pad and the substrate. An electrolytic slurry containing abrasive particles is flowed over the substrate or the pad. A voltage is applied between the polishing pad and the substrate to perform electropolishing of the substrate.
These and other features and advantages of the present invention are described below with reference to the drawings.
REFERENCES:
patent: 6096648 (2000-08-01), Lopatin et al.
patent: 6242343 (2001-06-01), Yamazaki et al.
patent: 6285035 (2001-09-01), Taravade
patent: 6315883 (2001-11-01), Mayer et al.
patent: 6368190 (2002-04-01), Easter et al.
Berman Michael J.
Reder Steven E.
Beyer Weaver & Thomas LLP
Hail III Joseph J.
LSI Logic Corporation
McDonald Shantese
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