Mechanical fixture for holding electronic devices under test...

Details Mechanical fixture for holding electronic devices under test... Mechanical fixture for holding electronic devices under test...

1999-10-15

2001-07-17

Brown, Glenn W. (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C269S050000, C269S2540CS, C269S2890MR, C269S900000, C269S903000

Reexamination Certificate

active

06262582

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
Not Applicable
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the mechanical fixtures for holding electronic devices under test, and more particularly the present invention relates to a mechanical fixture that can adjust the device being held in X, Y, Z and theta (&THgr;) direction while accommodating several hundred of pounds of force in the Z-direction.
2. Description of the Related Art
The density of semiconductor electronics increases every year. One known postulate in the field of semiconductor manufacturing is Moore's Law which predicts every 18 months the density of semiconductor circuitry doubles. Besides the obvious decrease in size for semiconductor devices, the number of transistors or gates that can be offered in a given die size continues to grow. This increase density allows for more complex circuitry to be eveloped. And although the increase in semiconductor density is very desirable it is not without its shortcomings.
One shortcoming is the increase in the density of input and output (I/O) points for a given circuit. It is not uncommon for highly density package to have hundreds and even thousands of I/O points. Besides providing communication with other devices, these I/O points provide an interface back to the circuitry for testing.
In order to ensure the devices on a semiconductor module function properly, testing on the semiconductor module, prior to dicing is often performed. Testing is typically done by applying signals across a wide frequency range to preselected inputs to see if a predetermined output signal is generated. Using various signal frequencies on the inputs, i.e., from D.C. (i.e., zero frequency) for the determination of simple breaks to high frequency A/C signals to determination of high impedance breaks, the circuitry on the devices can be tested.
Probing is one type of commonly used testing for semiconductors. Probing is where one or more probe inputs are directed to inputs of the device I/O and one or more sets of probe outputs are directed to outputs of the device I/O. Typically the probing is done with mechanical probes that are directed using servo systems to predefined locations on the semiconductor device. However, as the density of the I/O increases, the physical mechanical limitations of the probes become a limiting factor. For instance, in some highly integrated devices it is not uncommon to have over 1800 points of I/O in a 2 inch by 2 inch square area. The accurate placement of probes in an adjacent set of I/O points becomes problematic. To overcome this physical limitation, designers of test equipment use intermediate probe cards that have interconnects such as spring loaded pins, called pogo pins, that contact the I/O on the device. These probe cards which are larger than the device being tested provide an area that is larger for the probes to contact. However, as the density of the semiconductors devices increases, the density of the probe card I/O points that contact the I/O on the device must also increase.
In fact for very dense integrated circuits, it is common to have several levels of intermediate cards that physically fan out the I/O from the semiconductor device under test to the probe areas. Several levels of intermediate cards are often necessary to provide the proper mechanical fan out of the I/O points of the wafer being tested to the probe areas. The cards and substrates used to physically fan out the I/O to a larger probe area are often referred to as “space transformers.” Turning now to
FIG. 1
, shown is an elevational view
100
of a semiconductor wafer
102
having a plurality of semiconductor devices (not shown) with I/O points (not shown). Each I/O point has an interconnect wire
104
(not shown to scale) from the wafer
102
electrically attached to the topside
110
of substrate
106
. The underside
114
of the substrate
106
provides signals to the semiconductor wafer
102
for input such as power, ground and other operating signals. A probe card
116
provides an interposer of electronic signals from a test head
118
up through the underside of the substrate
106
. The test head
118
consists of a series of spring loaded pins (not shown), called pogo pins, that mate with the probe card
116
. The force necessary to hold the substrate
106
to the probe card
116
onto pogo pins
118
to ensure a good electrical connection can be very large. In fact, it may be common for the force to exceed 500 pounds in cases where there are several hundred pogo pins to mate against securely.
The substrate
106
has probe area
114
which allows a mechanical probe to read signals that are being applied to one or more devices on the semiconductor wafer
102
that is being delivered signals from the test head
118
. This allows the testing of one or more devices simultaneously on the semiconductor wafer
118
.
The alignment of the substrate
106
to the probe card
116
and test head
118
is critical. In fact, all the directions (i.e., X, Y, Z, and &THgr;) relative to the substrate
106
and the card
116
must be compensated.
Accordingly, a need exists for a mechanism to hold the substrate
106
securely under several hundred pounds of pressure in the Z-direction, while being compliant in the X, Y, Z, and &THgr;) directions.
Still, another problem that exists for a mechanism to hold the substrate
106
securely in place without sacrificing any of the underside area
114
of the substrate
106
being mounted on the probe cards
116
, so as to maximize the area for contact pogo pins. The area for the topside
110
of the substrate
106
is Key as well. The topside
110
area needs to be maximized for connections with the Wafer
102
. Accordingly, a need exists for a mechanism to hold the substrate
106
in a compliant manner without giving up any underside area
114
or topside
110
real-estate on the substrate
106
.
SUMMARY OF THE INVENTION
Briefly, in accordance with the present invention, described is a fixture to hold an electronic substrate having probe areas on a top surface. The top surface of the electronic substrate is left open to provide a maximum area to couple interconnect wires for a device under test. In addition, a bottom surface of the substrate is left open to provide a maximum area to couple with a probe card in one embodiment, or a test head in another embodiment. This open bottom and open top minimize the mechanical interference with electrical connections.
The substrate is planarized to a frame by one or more clamps that are attached to the frame. The clamps provide adjustment of the pressure down on the substrate in a Z-axis direction which is normal to the top surface of the substrate for providing a good connection with a planar card. In addition, the clamps provide adjustment in an X-Y plane parallel to the frame and rotational correction about the Z-axis.


REFERENCES:
patent: 4688870 (1987-08-01), Egawa et al.
patent: 4809917 (1989-03-01), Tsuchiya
patent: 5099393 (1992-03-01), Bentlage et al.
patent: 5106451 (1992-04-01), Kan et al.
patent: 5148103 (1992-09-01), Pasiecznik, Jr.
patent: 5177439 (1993-01-01), Liu et al.
patent: 5408190 (1995-04-01), Wood et al.
patent: 5416429 (1995-05-01), McQuade et al.
patent: 5506512 (1996-04-01), Tozawa et al.
patent: 5584711 (1996-12-01), Arai et al.
patent: 5623214 (1997-04-01), Pasiecznik, Jr.
patent: 5672977 (1997-09-01), Yamada
patent: 5804983 (1998-09-01), Nakajima et al.
patent: 5828225 (1998-10-01), Obikane et al.
patent: 5834842 (1998-11-01), Majumdar et al.
patent: 5861759 (1999-01-01), Bialobrodski et al.
patent: 5892366 (1999-04-01), Byers
patent: 5897108 (1999-04-01), Gordon et al.

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