Measuring the 3 dB frequency bandwidth of a phase-locked loop

Details Measuring the 3 dB frequency bandwidth of a phase-locked loop Measuring the 3 dB frequency bandwidth of a phase-locked loop

2006-09-05

2006-09-05

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C331S016000

Reexamination Certificate

active

07102401

ABSTRACT:
The 3 dB frequency bandwidth of a phase-locked loop (PLL) is determined by measuring the frequency of a voltage controlled oscillator (VCO) signal when an up charging current is applied, measuring the frequency of the VCO signal when a down charging current is applied, and then using the two frequency measurements to calculate the 3 dB frequency bandwidth of the PLL. The up and down charging currents can be applied through a charge current switch system and the frequency measurements can be made with a frequency counter, both of which are monolithically integrated with the PLL. The technique for measuring the 3 dB frequency bandwidth can be applied to a first order or a second PLL. When applied to a second order PLL, the technique includes an initial frequency centering operation.

REFERENCES:
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patent: 6557416 (2003-05-01), Chang et al.
patent: 2005/0068111 (2005-03-01), Kasahara et al.
Burbidge, Martin John, Tijou, Jim, Richardson, Andrew, “Techniques for Automatic On Chip Closed Loop Transfer Function Monitoring For Embedded Charge Pump Phase Locked Loop”, IEEE, 1530-1591/Mar. 2003.
Greshishchev, Yuriy, “SiGe Clock and Data Recovery IC with Linear-Type PLL for 10-Gb/s SONET Application” IEEE Journal of Solid-state Circuits, vol. 35, No. 9, Sep. 2000.
Hajimiri, Ali, “Noise in Phase-Locked Loops [Invited]” IEEE, 0-7803-6742-1/01, 2001.

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