Measuring pulse edge delay value relative to a clock using...

Details Measuring pulse edge delay value relative to a clock using... Measuring pulse edge delay value relative to a clock using...

2007-06-05

2007-06-05

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By pulse coincidence

C327S031000, C327S038000

Reexamination Certificate

active

11128775

ABSTRACT:
A pulse width measurement system is provided with components in an FPGA so that pulse widths can be measured that are smaller than the frequency limits of the FPGA system clock. For the measurement, an incoming pulse is fed into the FPGA to many (e.g. 32) I/O inputs in parallel. Each parallel input is then provided to a programmable delay device with each delay configured to a different ascending delay value. The input transition time is then detected by converting the outputs from the delay devices into data indicating the timing information. In one embodiment the outputs of the delay devices address data stored in BRAMs for later processing in the FPGA to determine the timing information.

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Xilinx, Inc.;Virtex-4 FPGA Handbook; Published Aug. 2004; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 355-358.

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