Measuring method and device for fault analysis of digital transm

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371 51, 375 10, G06F 1100, H04L 120

Patent

active

051365910

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

By the fault analysis of digital transmission paths, the influence of faults on the transmission paths is detected. Faults in the transmission of binary data have the effect that a transmitted logic "1" is received as "0" and vice versa. Such transmission errors are recognized through fault analysis in pulse code-modulated (PCM) systems by comparison of a received serial data stream with a transmitted data stream as reference data stream. Generally the transmitted data stream consists of apparently random binary sequences (quasi-random sequences), which are generated for example by means of a regenerative shift register at the site of transmission and reception. Now if in the comparison of the received data stream with the reference data stream bits transmitted error-free are marked by a "0" and bits transmitted wrong by a "1", one obtains at the output of the transmission path the "bit error pattern." In the evaluation of such bit error patterns it is then possible, for one thing, by simply viewing them, to recognize sensitive points of the transmission line relative to certain transmission patterns, and for another, by further processing of the bit error pattern in mathematical algorithms, statements can be made about stochastic and systematic transmission errors for determining the causes thereof.


SUMMARY OF THE INVENTION

The invention relates to a measuring method for fault analysis of digital transmission paths by detection of a bit error pattern, produced at the output of the respective transmission path, which in the error analysis is applied to an evaluator, with in which evaluation device, pattern, storing of the data blocks up to their unloading.
Such a measuring method is known for example from the paper "Detection of error pattern in the transmission of digital signals" read by Ernst Russ (Research Institute of the German Federal Postal Service) on the occasion of the "Third International Zurich Seminar on Digital Communication" in 1974 (published in "1974 International Zurich Seminar on Digital Communications, 12th-15th March 1974 Proceedings"). In this measuring method, error bits and error-free bits of the observed bit error pattern as counted in the first measuring mode within the counter unit with a first counter, the division into count sections occurring as a function of the alternation between error bits and error-free bits. The length of the individual count sections is recorded in a second counter belonging to the counter unit. The bit error pattern is thus combined to data blocks which contain information about the number and location of the transmitted error bits and error-free bits. When all counter digits of the first counter are occupied, output of its reading together with the reading of the second counter to a recirculating memory is brought about. This recirculating memory causes adaptation of the data transmission rate to the evaluation rate. When this recirculating memory is fully loaded, switching from the first to the second measuring mode takes place, in which, however, only a bit error count takes place, until the recirculating memory has been completely emptied. In the second measuring mode, therefore, only purely quantitative statements can be made (bit error rate), there is not information about the location of the individual error bits in the bit error pattern. Moreover, the known measuring method is suitable only for relatively low data transmission speeds, as the individual bits are always counted, pushed serially into the recirculating memory, and transported therein. Faster transmission speed exceed this processing speed.
As distinguished therefrom, the measuring method according to the invention is characterized in that error pattern are counted as data blocks into several counters arranged parallel side by side as a counter unit, where adjacent counter, free spaces as data blocks in the individual counters coincides with the access to the data blocks by the evaluator.
Advantageously the data reduction by formation of data blocks

REFERENCES:
patent: 3596245 (1971-07-01), Finnie et al.
patent: 3689884 (1972-09-01), Tew, Jr.
patent: 3956601 (1976-05-01), Harris et al.
patent: 3971920 (1976-07-01), Johnson
patent: 4022988 (1977-05-01), Lentz et al.
patent: 4580274 (1986-04-01), Debany, Jr. et al.
patent: 4688207 (1987-08-01), Yoshimoto

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