Measuring jitter of high-speed data channels

Details Measuring jitter of high-speed data channels Measuring jitter of high-speed data channels

1999-10-17

2003-12-09

Tran, Khai (Department: 2631)

Pulse or digital communications

Testing

Phase error or phase jitter

Reexamination Certificate

active

06661836

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to measurement of high-speed data channels, particularly measurement of jitter in clock signals using self-triggered undersampling techniques.
2. The Prior Art
In serial data communication standards such as Ethernet and ATM (speed range from 100 Mbps to 622 Mbps) or the higher speed new communication standards such as Fibre Channel, Firewire (S800 and S1600) and GigaBit Ethernet, the data and clock are embedded within the signal codes. Because of these characteristics the receiver must have special clock recovery circuitry (implemented with a phase-locked loop (PLL)), that would extract the data and clock from the “analog” symbols received through the media. These clock recovery circuits are sensitive to input jitter (time distortion) and level distortion. To guarantee proper data reception in any network the transmitter must meet a certain budget of transmitted jitter. Typical measurements in ATE systems use a GPIB instrument which can be slow, or a built in time measurement unit which can have limited bandwidth relative to the Gigabit data speed ranges.
Jitter in High Speed Data Communication Channels
Jitter is a critical parameter in high speed data communication channels. Jitter compliance is required for the transmitter and receiver in a communication system. The transmitter must meet a certain error budget of allowable jitter to be introduced into the network. The receiver must tolerate a certain amount of jitter in the received signal. See, for example,
FIG. 1A
which shows an example of a proposed jitter tolerance specification from JITTER WORKING GROUP TECHNICAL REPORT REV. 1.0, DRAFT E, May 27, 1997. In high speed communications the clock and data are embedded into the same physical signal. Thus, clock recovery circuitry is required on the receiver. This clock recovery circuitry employs phase-locked loops (PLL) that are sensitive to input jitter. Excessive jitter could cause errors in the data recovery impacting the bit error rate (BER) and the integrity of the overall network. Test techniques have been described for characterizing the jitter tolerance of the receivers. B. KULP,
Testing and Characterizing Jitter in
100
BASE
-
TX and
155.52
Mb/s ATM Devices with a Gsamples/s AWG in an ATE System
, International Test Conference, 1996, Paper 5.1, pp. 104-111. The subject of this paper is the characterization of the transmitting device jitter.
Similar serial data techniques and parameters also apply to hard disk drive read/write channels. In this case the serial data and embedded clock information is stored on and retrieved from a magnetic medium rather than being transmitted over cable; however, the sensitivity to jitter is similar.
Jitter sources could come from power supply noise, thermal noise from the PLL components and limited bandwidth of the transmitter (affecting mostly the Data Dependent Jitter-DDJ). The media through which the data is being transmitted could also add jitter. All of the above should be compensated for at the receiver side.
High speed communication standards specify the jitter budget allowed for the transmitter and its components, e.g., draft proposed X3 Technical Report—Fibre Channel—Methodologies for Jitter Specification, ANSI TRx3.xxx-199x Revision 1.0 Draft E, May 27, 1997. These jitter components consist of: DDJ—Data Dependent Jitter, RJ—Random Jitter, and DCD—Duty Cycle Distortion. Though the classification of jitter is critical for characterization and design validation, in the production environment the focus is on overall jitter.
Spectrum Analyzer Measurement
An analog spectrum analyzer can be used to measure the jitter of a signal in the frequency domain in terms of the phase noise. For this measurement the jitter is modeled as phase modulation. For example, a sine wave signal is represented as a perfect sine wave with amplitude and phase modulation:
v
(
t
)=
a
(
t
)sin(&ohgr;+&thgr;(
t
))
With a spectrum analyzer one can measure the power of the signal as a function of frequency with wide dynamic range, however one cannot distinguish between the amplitude and phase modulation components. A common assumption made when using a spectrum analyzer to measure jitter is that the amplitude modulation component of the signal is negligible. This assumption may be valid for signals internal to a pure digital system where undistorted square waves or pulses are the norm. This assumption is typically not true for a serial communication or data channel. Isolating the noise from the actual signal frequency components and translating that into jitter is non-trivial.
Real-time Tinie-interval-analyzer Measurements
This technique measures the time interval between a reference voltage (Vref) crossing of the transmitted signal. There is no need for an abstract model of the signal when using this technique because the time intervals are measured directly. The real-time time-interval analyzer gives complete knowledge of the nature of the jitter and the components of the jitter. With this measurement technique the position and time of every edge is measured, thus allowing statistical space and frequency-based models of the signal, as well as absolute peak-to-peak measurements. The clear advantages of this technique are the facts that there are no skipped edges and the measurement acquisition time is limited only by the signal itself In practice, instrumentation that has the necessary acquisition rate and resolution to test gigabit data rates (as seen with Firewire and Fibre Channel) does not exist.
Repetitive Start/Stop Time Measurements
This is a common technique that gives high resolution and accuracy using a direct time measurement. Time measurements are made by starting a counter on the first occurrence of an edge, and stopping the counter on the next edge. Enhancements to this technique include skipping multiple edges for cumulative measurements, comparing two different signals, and time interpolation for achieving resolution greater than the counter clock period. Re-triggering of the time interval measurement normally requires a significant dead time, particularly when time interpolation is used. After collecting many of these time interval measurements, post processing is applied to extract statistical parameters and jitter components. This technique has been used to good effect in automatic test equipment (ATE) to measure jitter of low frequency clocks (<100 MHz) or in some bench top instrument implementations that include special software features for jitter components characterization, such as the DTS-2075 instrument from Wavecrest Corporation. See TEST LIST OPTION USERS GUIDE, Wavecrest Corporation, Edina, Minn., March 1997, 45 pages.
Oscilloscope Based Histogram Measurements
This method is based on time-base analysis of the repetition of an edge in reference to a trigger (self trigger, or external trigger). The actual analog values of the signal are measured (either in real time, or undersampled equivalent time), and an overlay history of the signal is accumulated and displayed. High and low voltage thresholds, multiple time interval windows, and the number of samples to be acquired are defined. A histogram is produced according to the number of samples that fall into each of the time/voltage windows, as indicated in FIG.
1
B. Enhancements to this technique had been performed by post-processing the real-time captured analog waveform with advanced filtering to achieve fine accuracy and cycle-to-cycle jitter contributions, M. K. WILLIAMS, Accuracy in M1/720
Time Interval Measurement Systems
, ASA Tech Brief 95-38, ASA Doc #96-1, Amherst Systems Associates, Inc., Amherst, Mass., 1997, 7 pages.
Functional Test VLSI ATE Method
This method is based on developing a histogram of binary comparisons as an Automatic Test Equipment (ATE) system strobe signal is swept across a Device Under Test (DUT) signal transition in time. The DUT signal is strobed repeatedly and the pass/fail results are stored in computer memory and later used to create a histogram that

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