Measuring a minimum lock frequency for a delay locked loop

Details Measuring a minimum lock frequency for a delay locked loop Measuring a minimum lock frequency for a delay locked loop

2000-06-20

2002-12-31

Hoff, Marc (Department: 2857)

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

C702S116000, C702S126000, C702S176000, C702S177000

Reexamination Certificate

active

06502050

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field Of the Invention
This invention relates to testing integrated circuits (ICs), specifically field programmable gate arrays (FPGAs).
2. Description of the Related Art
Highly complicated field programmable gate array integrated circuits have become common in electronic system design. One important component of modern FPGAs, such as the Virtex™ family by Xilinx®, Inc., are stable locked loops such as the delay lock loop (DLL). The Virtex family of FPGAs is described on pages 3-1 to 3-23 of “The Programmable Logic Data Book 1999” (hereinafter the Xilinx Data Book), which pages are incorporated herein by reference. DLLs are described in Xilinx Application Note XAPP132, “Using the Virtex Delay-Locked Loop” (May 23, 2000, version 2.2), available from Xilinx, Inc., which is incorporated herein by reference.
The all-digital DLL of the Virtex family of FPGAs eliminates clock propagation delay and skew between a clock input to the FPGA device and the internal clock distribution network within the device. Additionally, the DLL eliminates skew between the various output clock signals distributed throughout the device.
FIG. 1
illustrates DLL
100
, comprised of delay element
110
, which is typically a programmable delay line, control element
120
, feedback loop
130
, and clock distribution network
140
. The DLL
100
monitors the input clock signal at clock terminal
150
(i.e., the clock signal supplied to the DLL from a source typically external to the FPGA device) and the clock distribution network
140
. Control element
120
automatically adjusts delay element
110
so that clock edges reach the FPGA's internal flip-flops (not shown) in clock distribution network
140
exactly one clock period after they arrive at clock terminal
150
. This closed-loop system effectively eliminates clock distribution delay by ensuring that clock edges arrive at internal flip-flops in synchronization with clock edges arriving at the DLL input (i.e., at clock terminal
150
).
An important parameter for understanding the design and use of a DLL is the minimum clock frequency at which the DLL will lock, i.e., the minimum input clock frequency at which the delay element effectively compensates for timing delays.
In the production and testing of FPGAs, the manufacturer needs to verify that the lock frequency of each DLL in the chip meets certain specifications. As currently known in the art, one technique for testing and measuring this frequency is to use a stable external reference frequency generator that directly drives the DLL under test. The frequency of the external generator is swept from a high to a low value and the lock signal coming out of the DLL is observed for transition from the locked to the unlocked state. The frequency at which this transition takes place is the minimum lock frequency.
This prior art method requires numerous external devices and measurement systems. Additionally, this method requires the ability to make difficult connections directly to the DLL circuit within the chip. A further drawback is that the production environment in which FPGAs are tested is extremely noisy in terms of electrical interference. Therefore, it is very difficult to generate a stable, jitter-free frequency reference against which one can measure the DLL lock frequency.
What is needed is a low-noise method of testing a DLL such that its lock frequency can be determined. Such a technique must operate quickly and inexpensively in accordance with the needs of modern, high volume manufacturing systems.
SUMMARY OF THE INVENTION
The present invention is directed to a method and structure for measuring the minimum lock frequency of a delay locked loop (DLL) within a programmable integrated circuit device such as a field programmable gate array (FPGA). This structure requires only that the device be temporarily configured such that one DLL block is programmed as a ring oscillator (RO) and connected to the input terminal of a second DLL (the DLL under test). The ring oscillator thus forms a programmable frequency source for driving the DLL under test. In one embodiment of the present invention, the RO is fed directly to the DLL under test. In an alternate embodiment of the present invention, the ring oscillator DLL is connected to the DLL under test through a divider to provide a lower DLL drive frequency.
To test the DLL, the ring oscillator frequency is decreased until the DLL under test fails to lock. The frequency of the ring oscillator DLL at that point is measured by comparing it to the frequency of an external clock source (such as a crystal oscillator) using two counters. The counters are implemented within the programmable IC (e.g., the field programmable gate array) in one embodiment of the present invention. A first counter counts pulses from the external clock source. A second counter counts pulses from the ring oscillator. Both counters are allowed to run for a period of time. The frequency of the ring oscillator at the lower lock limit of the DLL is proportional to the ratio of the two counts.


REFERENCES:
patent: 6081147 (2000-06-01), Okajima
patent: 6295328 (2001-09-01), Kim et al.
patent: 6337601 (2002-01-01), Klemmer
patent: 6348839 (2002-02-01), Aramaki
patent: 2002/0021179 (2002-02-01), Ooishi et al.
“The Programmable Logic Data Book 1999”, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, pp. 3-1 to 3-23.
Xilinx Application Note XAPP132, “Using the Virtex Delay-Locked Loop”, (May 23, 2000, version 2.2), available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, pp. 1-15.

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