Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing
Reexamination Certificate
2011-04-19
2011-04-19
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
C716S050000, C716S054000, C716S122000
Reexamination Certificate
active
07930660
ABSTRACT:
Implementations are presented herein that relate to a standard cell including a measuring structure for controlling process parameters during manufacture of an integrated circuit. A standard cell is formed in a plurality of material layers of an integrated circuit to perform part of a function of the integrated circuit, wherein the plurality of material layers is configured to be patterned by a plurality of mask layers during manufacture of the integrated circuit, wherein the standard cell includes a measuring structure that is placed within boundaries of the standard cell, wherein the measuring structure includes at least one feature in at least one of the plurality of material layers and the plurality of mask layers, wherein the at least one feature is configured to provide measurement results in order to control process parameters during manufacture of one of the material layers and mask layers.
REFERENCES:
patent: 2002/0155363 (2002-10-01), Cote et al.
patent: 2004/0248016 (2004-12-01), Lucas et al.
patent: 2005/0044522 (2005-02-01), Maeda
patent: 2006/0294491 (2006-12-01), Becker
patent: 2007/0011639 (2007-01-01), Pitts
patent: 2007/0278525 (2007-12-01), Acharya
patent: 2009/0101940 (2009-04-01), Barrows et al.
Deppe Roswitha
Lutz Walther
Ruderer Erwin
Infineon - Technologies AG
Siek Vuthe
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